DIRECTORY CD, Core, CoreBlock, CoreFrame, CoreGeometry, CoreInstCell, CoreOps, CoreClasses, CoreName, IO, PW, PWC; CoreInstCellImpl: CEDAR PROGRAM IMPORTS CoreBlock, CoreFrame, CoreClasses, CoreGeometry, CoreOps, CoreName, IO, PW, PWC EXPORTS CoreInstCell = BEGIN specificGenericCellClass: PUBLIC Core.CellClass _ CoreOps.SetClassPrintProc[ class: NEW[ Core.CellClassRec _ [name: "SpecificGeneric", recast: Recast]], proc: ClassPrintProc]; ClassPrintProc: CoreOps.PrintClassProc = { cell: Core.CellType _ NARROW [data]; out.PutF["\nSpecificGeneric Instance of: %g", IO.rope[CoreName.CellNm[cell].n]]}; Recast: PUBLIC Core.RecastProc = { name: Core.ROPE _ CoreName.CellNm[me].n; log.PutF["\nRecasting Specific Generic: %g", IO.rope[name]]; new _ CoreBlock.AbutCellList[name, left, LIST[me]]}; SpecificGeneric: PUBLIC PROC[generic: Core.CellType, proc: CoreInstCell.RenameProc] RETURNS [specific: Core.CellType] = { ctx: CoreName.Context _ CoreName.NewContext[]; internal: Core.Wire _ CoreOps.CreateWires[generic.public.size]; FOR index: INT IN [0..internal.size) DO aName: Core.ROPE _ CoreName.WireNm[generic.public[index] ].n; aName _ proc[aName]; internal[index] _ IF aName#NIL THEN CoreName.CtxWire [ctx, aName] ELSE CoreOps.CreateWires[0]; [ ] _ CoreBlock.AddWireSide [internal[index], CoreBlock.GetWireSide[generic.public[index]]]; ENDLOOP; IF generic.class # CoreClasses.recordCellClass AND generic.class # PWC.rotatedCellClass THEN Signal[]; specific _ NEW[Core.CellTypeRec _ [ class: specificGenericCellClass, public: internal, data: generic, properties: NIL ]]; ctx _ CoreName.KillContext[ctx]; CoreGeometry.PutObject[PWC.extractMode.decoration, specific, generic]; CoreBlock.PutCellSide [specific, all]; PWC.SetLayout[specific, $SpecificGenericLayout]}; SGLayout: PWC.LayoutProc = { genericObj: CD.Object _ PWC.Layout[NARROW[cellType.data]]; obj _ PW.ChangeOrientation[genericObj, original]}; SGDecorate: PWC.DecorateProc = { genericCell: Core.CellType _ NARROW[cellType.data]; name: Core.ROPE _ CoreName.CellNm[cellType].n; Visit: CoreOps.EachWirePairProc ~ { new: Core.ROPE _ CoreName.WireNm[publicWire].n; IF publicWire.size#0 THEN RETURN[TRUE, FALSE]; [ ] _ CoreBlock.AddWireSide[publicWire, CoreBlock.GetWireSide[actualWire]]; CoreGeometry.AddIndirectLazyPins[PWC.extractMode.decoration, publicWire, actualWire]}; log.PutF["\nDecorating Specific Generic: %g | %g", IO.rope[name], IO.rope[CoreName.CellNm[genericCell].n]]; [ ] _ CoreOps.VisitBinding [actual: genericCell.public, public: cellType.public, eachWirePair: Visit]}; Signal: SIGNAL = CODE; log: IO.STREAM _ CoreFrame.GetLog[]; [ ] _ PWC.RegisterLayoutAtom[$SpecificGenericLayout, SGLayout, SGDecorate] END. (CoreInstCellImpl.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. Created by Don Curry, February 1, 1986 2:43:22 pm PST Edited by Don Curry, February 21, 1987 11:00:50 am PST Last Edited by: Louis Monier February 10, 1987 5:43:30 pm PST Recast: PUBLIC Core.RecastProc = { name: Core.ROPE _ CoreName.CellNm[me].n; internal: Core.Wire _ CoreOps.CopyWire[me.public]; cell: Core.CellType _ me; public: Core.Wire _ CoreOps.CreateWires[cell.public.size]; actual: Core.Wire _ CoreOps.CreateWires[cell.public.size]; log.PutF["\nRecasting Specific Generic: %g", IO.rope[name]]; IF cell.public.size#internal.size THEN Signal[]; FOR index: INT IN [0..internal.size) DO actual[index] _ internal[index] ENDLOOP; FOR index: INT IN [0..internal.size) DO public[index] _ internal[index] ENDLOOP; new _ CoreClasses.CreateRecordCell[ public: public, internal: internal, instances: LIST [CoreClasses.CreateInstance[actual: actual, type: cell]]]; CoreBlock.PutCellSide [new, all]; CoreBlock.MergeSides [new]}; ELSE CoreOps.CreateWire[name: CoreName.ID["DeadEnd"]]; CoreGeometry.PutIR[PWC.extractMode.decoration, cellType, CD.InterestRect[genericObj]]; SGLayout: PWC.LayoutProc = { recast: Core.CellType; name: Core.ROPE _ CoreName.CellNm[cellType].n; log.PutF["\nRedefine Specific Generic: %g", IO.rope[name]]; recast _ CoreOps.Recast[cellType]; obj _ PW.ChangeOrientation[PWC.Layout[recast], original]; IF cellType.public.size#temp.public.size THEN Signal[]; FOR i: INT IN [0..cellType.public.size) DO wireNm: Core.ROPE _ CoreName.WireNm[cellType.public[i]].n; wire: Core.Wire _ CoreOps.FindWire[temp.public, wireNm]; IF wire=NIL THEN Signal[]; cellType.public[i] _ wire; ENDLOOP; CoreOps.FlushNameCaches[cellType.public]; cellType.class _ temp.class; cellType.data _ temp.data; CoreBlock.PutCellSide[cellType, all]}; ÊY˜šœ™Jšœ<™