<> <> <> DIRECTORY CoreCreate, CD, CDOrient, Basics, Core, CoreBlock, CoreGeometry, CoreIOIFUProps, CoreOps, CoreClasses, CoreFrame, CoreInstCell, CoreName, CoreProperties, HashTable, IO, PWC, Rope; CoreBlockImpl: CEDAR PROGRAM IMPORTS CD, CDOrient, Basics, CoreBlock, CoreOps, CoreFrame, CoreGeometry, CoreInstCell, CoreIOIFUProps, CoreName, CoreProperties, HashTable, IO, PWC, Rope EXPORTS CoreBlock = BEGIN OPEN CoreBlock; Wire: TYPE = Core.Wire; CellType: TYPE = Core.CellType; ROPE: TYPE = Core.ROPE; SidesProp: PROC RETURNS[ATOM] = {RETURN[CoreIOIFUProps.sides]}; Signal: SIGNAL[] = CODE; AddSide: PUBLIC PROC[new, old: Sides] RETURNS[Sides] = {RETURN[SidesFmWord[Basics.BITOR[SidesToWord[new], SidesToWord[old]]]]}; DelSide: PUBLIC PROC[new, old: Sides] RETURNS[Sides] = {RETURN[SidesFmWord[Basics.BITAND[Basics.BITNOT[SidesToWord[new]], SidesToWord[old]]]]}; OnSide: PUBLIC PROC[new, old: Sides] RETURNS[BOOL] = {RETURN[(Basics.BITAND[SidesToWord[new], SidesToWord[old]])#0]}; OtherSide: PUBLIC PROC[side: Sides] RETURNS[Sides] = {RETURN[SELECT side FROM bottom=>top, top=>bottom, left=>right, right=>left,ENDCASE=>none]}; SidesToWord: PUBLIC PROC[side: Sides] RETURNS[word: WORD] = {RETURN[LOOPHOLE[side]]}; SidesFmWord: PUBLIC PROC[word: WORD] RETURNS[side: Sides] = {RETURN[LOOPHOLE[Basics.BITAND[word, SidesToWord[all] ] ] ] }; GetCellSide: PUBLIC PROC[cell: CellType] RETURNS[side: Sides] = { refSides: REF Sides; IF cell=NIL THEN RETURN[none]; refSides _ NARROW[CoreProperties.GetCellTypeProp[cell, SidesProp[]]]; RETURN[IF refSides=NIL THEN none ELSE refSides^] }; PutCellSide: PUBLIC PROC[cell: CellType, side: Sides] = {CoreProperties.PutCellTypeProp[cell, SidesProp[], NEW[CoreBlock.Sides _ side]]}; GetWireSide: PUBLIC PROC[wire: Wire] RETURNS[side: Sides] = { refSides: REF Sides; IF wire=NIL THEN RETURN[none]; refSides _ NARROW[CoreProperties.GetWireProp[wire, SidesProp[]]]; RETURN[IF refSides=NIL THEN none ELSE refSides^]}; PutWireSide: PUBLIC PROC[wire: Wire, side: Sides] = { refSides: REF Sides; IF wire=NIL THEN RETURN; refSides _ NARROW[CoreProperties.GetWireProp[wire, SidesProp[]]]; IF refSides=NIL THEN CoreProperties.PutWireProp[wire, SidesProp[], NEW[CoreBlock.Sides _ side]] ELSE refSides^ _ side; FOR i: NAT IN [0..wire.size) DO PutWireSide[wire[i], side] ENDLOOP}; AddWireSide: PUBLIC PROC[wire: Wire, side: Sides] RETURNS[sameWire: Wire] = { refSides: REF Sides; IF wire=NIL THEN RETURN[NIL]; refSides _ NARROW[CoreProperties.GetWireProp[wire, SidesProp[]]]; IF refSides=NIL THEN refSides _ NEW[Sides _ none]; refSides^ _ AddSide[side, refSides^]; CoreProperties.PutWireProp[wire, SidesProp[], refSides]; FOR i: NAT IN [0..wire.size) DO wire[i] _ AddWireSide[wire[i], side] ENDLOOP; RETURN[wire]}; DelWireSide: PUBLIC PROC[wire: Wire, side: Sides] RETURNS[sameWire: Wire] = { refSides: REF Sides; IF wire=NIL THEN RETURN[NIL]; refSides _ NARROW[CoreProperties.GetWireProp[wire, SidesProp[]]]; IF refSides=NIL THEN refSides _ NEW[Sides _ none]; refSides^ _ DelSide[side, refSides^]; CoreProperties.PutWireProp[wire, SidesProp[], refSides]; FOR i: NAT IN [0..wire.size) DO wire[i] _ DelWireSide[wire[i], side] ENDLOOP; RETURN[wire]}; MergeSides: PUBLIC PROC[cell: CellType] = { first: Sides _ GetCellSide[cell]; last: Sides _ OtherSide[first]; hidden: Sides; data: CoreClasses.RecordCellType _ NARROW[cell.data]; visit: CoreOps.EachWirePairProc ~ { side: Sides _ GetWireSide[publicWire]; side _ DelSide[hidden, side]; [ ] _ AddWireSide[actualWire, side]}; IF data.size>1 AND first=none THEN Signal[]; FOR i: NAT IN [0..data.size) DO hidden _ IF i # 0 THEN first ELSE none; hidden _ AddSide[ IF (i+1) < data.size THEN last ELSE none, hidden]; [ ] _ CoreOps.VisitBinding[data[i].actual, data[i].type.public, visit] ENDLOOP; DeletePseudoPublics[cell]}; DeletePseudoPublics: PUBLIC PROC [cell: Core.CellType] = { publics: Core.Wires _ NIL; FOR i: INT DECREASING IN [0..cell.public.size) DO IF GetWireSide[ cell.public[i] ]#none THEN publics _ CONS[ cell.public[i], publics] ELSE log.PutF["\nRemoving pseudo public: %g", IO.rope[ CoreName.WireNm[cell.public[i]].n] ]; ENDLOOP; cell.public _ CoreOps.CreateWire[publics]}; RevInstances: PROC[list: CoreClasses.CellInstances] RETURNS[rev: CoreClasses.CellInstances] = { FOR list _ list, list.rest WHILE list#NIL DO rev _ CONS[list.first, rev] ENDLOOP}; AbutCellList: PUBLIC PROC[ name: ROPE, first: Sides, cellTypes: LIST OF CellType] RETURNS[cellType: CellType] = { temp: LIST OF CellType _ NIL; cts: LIST OF CellType _ NIL; data: CoreClasses.RecordCellType; <> <> <> < specificGeneric _ TRUE;>> < other _ TRUE ENDLOOP;>> <> FOR temp: LIST OF CellType _ cellTypes, temp.rest WHILE temp#NIL DO cts _ CONS[(IF temp.first.class=CoreInstCell.specificGenericCellClass THEN NARROW[ temp.first.data, CellType] ELSE temp.first ), cts]; ENDLOOP; IF first=left OR first=bottom THEN { temp: LIST OF CellType _ cts; cts _ NIL; FOR temp _ temp, temp.rest WHILE temp#NIL DO cts _ CONS[temp.first, cts] ENDLOOP}; cellType _ PWC.AbutList[ cts, (first=left OR first=right)]; [ ] _ CoreName.CellNm[cellType, name]; CoreBlock.PutCellSide[cellType, (SELECT first FROM left, right => left, ENDCASE => bottom)]; CoreBlock.MergeSides[cellType]; IF first=top OR first=right THEN { temp: LIST OF CellType _ cellTypes; cellTypes _ NIL; FOR temp _ temp, temp.rest WHILE temp#NIL DO cellTypes _ CONS[temp.first, cellTypes] ENDLOOP}; <> data _ NARROW[cellType.data]; FOR index: NAT IN [0..data.size) DO Visit: CoreOps.EachWirePairProc ~ { new: ROPE _ CoreName.WireNm[publicWire].n; IF publicWire.size#actualWire.size THEN Signal[]; IF publicWire.size#0 THEN RETURN[TRUE, FALSE]; <> <<{IF CoreName.WireNm[actualWire].n.Length[]#0 THEN Signal[]};>> [ ] _ CoreName.WireNm[actualWire, new]}; <> <> <> <> <> IF cellTypes.first.public.size#0 THEN [ ] _ CoreOps.VisitBinding [actual: data[index].actual, public: cellTypes.first.public, eachWirePair: Visit]; cellTypes _ cellTypes.rest ENDLOOP; EnsureUniqueNames[cellType]}; <> <> <> MergeCell: PUBLIC PROC[cellType: CellType] = { data: CoreClasses.RecordCellType _ NARROW[cellType.data]; FOR index: NAT IN [0..data.size) DO Visit: CoreOps.EachWirePairProc ~ { new: ROPE _ CoreName.WireNm[publicWire].n; IF publicWire.size#0 OR new.Length[]=0 THEN RETURN[TRUE, FALSE]; [ ] _ CoreName.WireNm[actualWire, new]}; IF data[index].type.public.size#0 THEN [ ] _ CoreOps.VisitBinding [actual: data[index].actual, public: data[index].type.public, eachWirePair: Visit] ENDLOOP; EnsureUniqueNames[cellType]}; phA: ROPE _ CoreName.RopeNm["PhA"]; phB: ROPE _ CoreName.RopeNm["PhB"]; GND: ROPE _ CoreName.RopeNm["GND"]; VDD: ROPE _ CoreName.RopeNm["VDD"]; VBB: ROPE _ CoreName.RopeNm["VBB"]; <<>> <> <> EnsureUniqueNames: PROC[cellType: CellType] = { publics: CoreName.Context _ CoreName.NewContext[]; -- public name to wire deletedPublics: HashTable.Table _ HashTable.Create[]; -- wires internal: CoreName.Context _ CoreName.NewContext[]; -- internal name to wire iVersion: HashTable.Table _ HashTable.Create[]; -- internal name to version data: CoreClasses.RecordCellType _ NARROW[cellType.data]; ResolveNameConflicts: PROC[root: Wire, mergeConflicts: BOOL _ FALSE] = { CoreOps.FlushNameCaches[root]; FOR i: INT IN [0..root.size) DO IF root[i].size # 0 THEN ResolveNameConflicts[root[i], mergeConflicts] ELSE { old: Wire _ root[i]; wNm: ROPE _ CoreName.WireNm[old].n; regPublic: Wire _ CoreName.CtxNameToWire[publics, wNm]; regInternal: Wire _ CoreName.CtxNameToWire[internal, wNm]; alreadyMerged: BOOL _ HashTable.Fetch[deletedPublics, old].found; IF wNm.Length[]=0 THEN LOOP; -- no conflicts possible IF regInternal=old THEN LOOP; IF regPublic#NIL AND mergeConflicts OR alreadyMerged THEN { root[i] _ regPublic; IF alreadyMerged THEN LOOP; [ ] _ HashTable.Store[deletedPublics, old, old]; [ ] _ AddWireSide[root[i], GetWireSide[old]]; CoreGeometry.AddIndirectLazyPins[PWC.extractMode.decoration, root[i], old]; LOOP}; SELECT wNm FROM phA, phB, GND, VDD, VBB => Signal[]; ENDCASE; IF regInternal=NIL THEN {[ ] _ CoreName.CtxRegisterWire[internal, old]} ELSE { last: REF INT _ NARROW[HashTable.Fetch[iVersion, wNm].value]; IF last=NIL THEN {[ ] _ HashTable.Store[iVersion, wNm, NEW[INT _ 0]]; LOOP}; last^ _ last^ +1; []_CoreName.WireNm[old, wNm.Cat[IO.PutFR["!%g",IO.int[last^]]]]}} ENDLOOP}; Visitor: PROC [wire: Wire] = { [ ] _ CoreName.CtxRegisterWire[publics, wire]; [ ] _ CoreName.CtxRegisterWire[internal, wire]}; log.PutF["\nEnsure unique wire names for: %g ", IO.rope[CoreName.CellNm[cellType].n]]; [ ] _ CoreOps.VisitRootAtomics[cellType.public, Visitor]; ResolveNameConflicts[root: cellType.public, mergeConflicts: TRUE]; FOR i: INT IN [0..data.size) DO ResolveNameConflicts[root: data[i].actual, mergeConflicts: FALSE] ENDLOOP; ResolveNameConflicts[root: data.internal, mergeConflicts: FALSE]; cellType.public _ CoreName.WireFromCtx[publics]; -- flatten and reorder <> HashTable.Erase[iVersion]; HashTable.Erase[deletedPublics]; publics _ CoreName.KillContext[publics]; publics _ CoreName.KillContext[internal]}; <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <<[]_CoreName.WireNm[old, wNm.Cat[IO.PutFR["!%g",IO.int[last^]]]];>> <> <> <> <> <> <> <> <<[]_CoreName.WireNm[old, wNm.Cat["!0"]];>> <<[ ] _ HashTable.Store[iOnlys, wNm, NEW[INT _ 1]]; LOOP} };>> <> <<[ ] _ HashTable.Store[deletedPublics, old, old];>> <> <<[ ] _ AddWireSide[root[i], GetWireSide[old]];>> <> <> <> <> <<[ ] _ CoreOps.VisitRootAtomics[cellType.public, VisitPublics];>> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> < TRUE, bottom, top => FALSE, ENDCASE => ERROR;>> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <<[ ] _ AddWireSide[parentPublic, DelSide[inSides, sides]] } };>> <> <> <> <> <<[ ] _ CoreOps.VisitBinding>> <<[actual: list.first.actual, public: list.first.type.public, eachWirePair: eachWirePair];>> <> <> <> <> <> <> <> <> <> < { }; ENDCASE => {>> <> <> <> <> <> <> <> <> <> <> <> DelPAInternalOnlys: PROC[context: CoreName.Context, ais: LIST OF PWC.AbutInstance] = { IsPublic: PROC[wr: CoreCreate.WR] RETURNS[BOOL] = {name: ROPE _ NARROW[wr]; RETURN[CoreName.CtxNameToWire[context, name]#NIL]}; FOR ais _ ais, ais.rest WHILE ais#NIL DO -- two LOOPs to avoid CONSing pas: LIST OF CoreCreate.PA; DO -- remove internal onlys from first of list IF ais.first.pas=NIL THEN GOTO Exit; IF IsPublic[ais.first.pas.first.actual] THEN EXIT; ais.first.pas _ ais.first.pas.rest; REPEAT Exit => LOOP; ENDLOOP; pas _ ais.first.pas; WHILE pas.rest#NIL DO -- remove internal onlys from rest of list IF IsPublic[pas.rest.first.actual] THEN pas _ pas.rest ELSE pas.rest _ pas.rest.rest ENDLOOP; ENDLOOP}; checking: BOOL _ TRUE; OutSides: PROC[index, size: INT, first: Sides] RETURNS[ outSides: Sides _ all] = { nextInSide, lastInSide: Sides; SELECT first FROM left => {nextInSide _ right; lastInSide _ left}; bottom => {nextInSide _ top; lastInSide _ bottom}; right => {nextInSide _ left; lastInSide _ right}; top => {nextInSide _ bottom; lastInSide _ top}; ENDCASE => Signal[]; IF index#0 THEN outSides _ DelSide[lastInSide, outSides]; IF index+1#size THEN outSides _ DelSide[nextInSide, outSides]}; <<>> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> < RevInstances[instances], ENDCASE => instances;>> <> <> <> < {obj _ PW.AbutListX[objs]; newFirst _ left};>> < {obj _ PW.AbutListY[objs]; newFirst _ bottom};>> < ERROR;>> <> <<[ ] _ CoreName.CellNm[cellType, name];>> <> <1 AND first=none THEN Signal[];>> <> < RevInstances[instances], ENDCASE => instances;>> <> <> <> <<[ ] _ CoreName.WireNm[actualWire, name]};>> <> <> <<[ ] _ CoreOps.VisitBinding>> <<[actual: data[index].actual, public: list.first.actual, eachWirePair: Visit];>> <> <> <> <> <> <> < PWC.SetAbutX[cellType];>> < PWC.SetAbutY[cellType];>> < Signal[] };>> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> < RevInstances[instances], ENDCASE => instances;>> <> <> <> < {obj _ PW.AbutListX[objs]; newFirst _ left};>> < {obj _ PW.AbutListY[objs]; newFirst _ bottom};>> < ERROR;>> <> <> <<[ ] _ CoreName.CellNm[cellType, name];>> <> <1 AND first=none THEN Signal[];>> <> < RevInstances[instances], ENDCASE => instances;>> <> <> <> <> <> <> <> <> <<[ ] _ HashTable.Store[publicSides, name, pubs];>> <<[ ] _ CoreName.WireNm[actualWire, name]};>> <> <> <> <> <<[ ] _ CoreOps.VisitBinding>> <<[actual: data[index].actual, public: list.first.actual, eachWirePair: Visit];>> <> <> <> <> <> <> <> < PWC.SetAbutX[cellType];>> < PWC.SetAbutY[cellType];>> < Signal[] };>> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> < PWC.SetAbutX[cellType];>> < PWC.SetAbutY[cellType];>> < Signal[] };>> MarkSides: PUBLIC PROC[cell: CellType, cap: Sides _ none] = { eachWireProc: PROC [wire: Wire] = {[ ] _ CoreBlock.PutWireSide[wire, DelSide[cap, GetWireLayoutSides[cell, wire] ] ]}; IF GetCellSide[cell]#none THEN RETURN; -- already done (ie. cached blank) [] _ CoreOps.VisitRootAtomics[cell.public, eachWireProc]; PutCellSide[cell, all]}; MySides: PROC[hisSides: CoreGeometry.Sides] RETURNS[mySides: Sides _ none] = { IF hisSides[left] THEN mySides _ CoreBlock.AddSide[mySides, left]; IF hisSides[right] THEN mySides _ CoreBlock.AddSide[mySides, right]; IF hisSides[top] THEN mySides _ CoreBlock.AddSide[mySides, top]; IF hisSides[bottom] THEN mySides _ CoreBlock.AddSide[mySides, bottom]}; GetWireLayoutSides: PUBLIC PROC[cell: CellType, wire: Wire] RETURNS[sides: Sides _ none] = { ir: CD.Rect _ PWC.InterestRect[cell]; eachPinProc: CoreGeometry.EachInstanceProc = {sides _ CoreBlock.AddSide[sides, MySides[CoreGeometry.GetSides[ir, instance]]]}; [] _ CoreGeometry.EnumeratePins[PWC.extractMode.decoration, wire, eachPinProc]}; GetInstSideLocSize: PUBLIC PROC [ob: CD.Object, inst: CD.Instance] RETURNS [side: CoreBlock.Sides, loc, size: INT] = { base: CD.Rect _ CD.InterestRect[ob]; rect: CD.Rect _ CDOrient.RectAt[inst.location, inst.ob.size, inst.orientation]; side _ none; IF base.y1 = rect.y1 THEN side _ AddSide[bottom, side]; IF base.x2 = rect.x2 THEN side _ AddSide[right, side]; IF base.y2 = rect.y2 THEN side _ AddSide[top, side]; IF base.x1 = rect.x1 THEN side _ AddSide[left, side]; loc _ SELECT side FROM left, right => rect.y1 - base.y1, top, bottom => rect.x1 - base.x1, ENDCASE => 0; size _ SELECT side FROM left, right => rect.y2 - rect.y1, top, bottom => rect.x2 - rect.x1, ENDCASE => 0}; log: IO.STREAM _ CoreFrame.GetLog[]; <<>> END.