DIRECTORY Core, CoreOps, CoreProperties, CoreRecordCells, IO; CoreRecordCellsImpl: CEDAR PROGRAM IMPORTS CoreOps, CoreProperties, IO EXPORTS CoreRecordCells = BEGIN OPEN Core, CoreRecordCells; recordCellClass: PUBLIC CellClass _ NEW[CellClassRec _ [name: "RecordCell", recast: NIL, write: Write, read: Read]]; Start: PROC = { CoreOps.RegisterCellClass[recordCellClass]; }; Write: WriteProc = { }; Read: ReadProc = { }; Print: PUBLIC PROC [cell: RecordCell, out: STREAM] = { InternalName: CoreOps.EachWireProc = { internal: ROPE _ NIL; FormInternalName: PROC [context: Wire] RETURNS [quit: BOOL _ FALSE] = { IF (quit _ notSubWires _ wire=context) THEN internal _ NARROW[CoreProperties.GetProp[from: context.properties, prop: $FullName]] ELSE IF context.elements#NIL THEN { FOR i:NAT IN [0..context.elements.size) DO quit _ FormInternalName[context: context.elements[i]]; IF quit THEN EXIT; ENDLOOP; }; }; [] _ FormInternalName[context: cell.internalWire]; IF notSubWires THEN IO.PutF[out, " %g", IO.rope[internal]]; }; IO.PutRope[out, "\nInternal wire:"]; CoreOps.PrintWire[cell.internalWire, out]; CoreOps.NameWire[wire: cell.internalWire, name: NIL]; FOR instList: LIST OF CoreRecordCells.Instance _ cell.instances, instList.rest UNTIL instList=NIL DO IO.PutF[out, "\n\nInstance: %g, type: %g", IO.rope[instList.first.name], IO.rope[instList.first.type.name]]; CoreProperties.PrintProperties[instList.first.properties, out]; IO.PutRope[out, "\nActual wire:"]; CoreOps.VisitWire[wire: instList.first.actualWire, eachWire: InternalName]; ENDLOOP; }; Start[]; END. ξCoreRecordCellsImpl.mesa Copyright c 1985 by Xerox Corporation. All rights reserved. Last Edited by: Barth, August 13, 1985 7:43:26 pm PDT Spreitzer, August 12, 1985 5:21:14 pm PDT Bertrand Serlet August 14, 1985 11:17:24 am PDT ΚV– "cedar" style˜codešœ™Kšœ Οmœ1™