CoreSequenceImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, September 30, 1985 4:03:07 pm PDT
Spreitzer, August 12, 1985 5:22:30 pm PDT
Bertrand Serlet October 2, 1985 12:28:42 pm PDT
DIRECTORY Core, CoreOps, CoreProperties, CoreRecord, CoreSequence, IO;
CoreSequenceImpl:
CEDAR
PROGRAM
IMPORTS CoreOps, CoreProperties, CoreRecord, IO
EXPORTS CoreSequence =
BEGIN OPEN Core, CoreSequence;
sequenceCellClass: PUBLIC CellClass ← NEW[CellClassRec ← [name: "Sequence", recast: Recast, write: Write, read: Read, properties: CoreProperties.Props[[CoreOps.printClassProcProp, NEW[CoreOps.PrintClassProc ← PropPrintClass]]]]];
Start:
PROC = {
CoreOps.RegisterCellClass[sequenceCellClass];
};
Recast: RecastProc = {
seqCell: SequenceCellType ← NARROW[me.data];
recCell: CoreRecord.RecordCellType ← NEW[CoreRecord.RecordCellTypeRec];
new ←
NEW[CellTypeRec ← [
name: me.name,
class: CoreRecord.recordCellClass,
publicWire: CoreOps.CopyWire[wire: me.publicWire],
data: recCell,
properties: CoreProperties.CopyProps[propList: me.properties]]];
recCell.internalWire ←
NEW[WireRec ← [
structure: sequence]];
recCell.internalWire.elements ← NEW[WireSequenceRec[new.publicWire.elements.size + seqCell.stitches.length]];
FOR w:
NAT
IN [0..new.publicWire.elements.size)
DO
recCell.internalWire.elements[w] ← new.publicWire.elements[w];
ENDLOOP;
FOR w:
NAT
IN [new.publicWire.elements.size..recCell.internalWire.elements.size)
DO
recCell.internalWire.elements[w] ← NEW[WireRec ← [structure: sequence]];
recCell.internalWire.elements[w].elements ← NEW[WireSequenceRec[ seqCell.count]];
ENDLOOP;
FOR cell:
NAT
IN [0..seqCell.count)
DO
newWire: Wire ← NEW[WireRec ← new.publicWire^];
newWire.elements ← NEW[WireSequenceRec[new.publicWire.elements.size] ← new.publicWire.elements^];
FOR seqWire:
NAT
IN [0..seqCell.length)
DO
newWire.elements[seqCell.sequence[seqWire]] ← newWire.elements[seqCell.sequence[seqWire]].elements[cell];
ENDLOOP;
FOR stitchWire:
NAT
IN [0..seqCell.stitches.length)
DO
internal: Wire;
IF cell < seqCell.count -1
THEN {
internal ← CoreOps.CopyWire[wire: seqCell.base.publicWire.elements[seqCell.stitches[stitchWire].source]];
recCell.internalWire.elements[stitchWire + new.publicWire.elements.size].elements[cell] ← internal;
newWire.elements[seqCell.stitches[stitchWire].source] ← internal;
};
IF cell > 0 THEN newWire.elements[seqCell.stitches[stitchWire].sink] ← recCell.internalWire.elements[stitchWire + new.publicWire.elements.size].elements[cell-1];
ENDLOOP;
recCell.instances ←
CONS[
NEW[CoreRecord.CellInstanceRec ← [
name: IF seqCell.base.name=NIL THEN NIL ELSE IO.PutFR["%g%g", IO.rope[seqCell.base.name], IO.int[cell]],
actualWire: newWire,
type: seqCell.base]],
recCell.instances];
ENDLOOP;
};
Create:
PUBLIC
PROC [design: Design, name:
ROPE ←
NIL, args: SequenceCellType]
RETURNS [cellType: CellType] = {
cellType ←
NEW[CellTypeRec ← [
name: name,
class: sequenceCellClass,
publicWire: CoreOps.CopyWire[wire: args.base.publicWire],
data: args]];
FOR i:
NAT
IN [0..args.length)
DO
wire: Wire ← cellType.publicWire.elements[args.sequence[i]];
IF wire.structure=sequence
THEN {
newSeqLength: NAT ← args.count * wire.elements.size;
newSeq: WireSequence ← NEW[WireSequenceRec[newSeqLength]];
base: Wire ← wire.elements[0];
FOR i:
NAT
IN [0..newSeqLength)
DO
newSeq[i] ← CoreOps.CopyWire[wire: base];
ENDLOOP;
cellType.publicWire.elements[args.sequence[i]].elements ← newSeq;
}
ELSE {
newWire: Wire ←
NEW[WireRec ← [
name: wire.name,
structure: sequence,
elements: NEW[WireSequenceRec[args.count]]]];
FOR i:
NAT
IN [0..args.count)
DO
wire.elements[i] ← CoreOps.CopyWire[wire: wire];
ENDLOOP;
cellType.publicWire.elements[args.sequence[i]] ← newWire;
};
ENDLOOP;
};
PropPrintClass: CoreOps.PrintClassProc = {Print[NARROW[data], out]};
Print:
PUBLIC
PROC [cell: SequenceCellType, out:
IO.
STREAM] = {
IO.PutF[out, "\n\nBase cell type: %g", IO.rope[cell.base.name]];
IO.PutF[out, ", count: %g", IO.int[cell.count]];
IO.PutRope[out, "\nstitch wires:"];
IF cell.stitches#
NIL
THEN
FOR stitch:
NAT
IN [0..cell.stitches.length)
DO
IO.PutF[out, " (%g, %g)", IO.rope[cell.base.publicWire.elements[cell.stitches[stitch].source].name], IO.rope[cell.base.publicWire.elements[cell.stitches[stitch].sink].name]];
ENDLOOP;
IO.PutRope[out, "\nsequence wires:"];
FOR seq:
NAT
IN [0..cell.length)
DO
IO.PutF[out, " %g", IO.rope[cell.base.publicWire.elements[cell[seq]].name]];
ENDLOOP;
};
Start[];
END.