CoreArrayCellClassImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, August 14, 1985 10:12:44 pm PDT
DIRECTORY Core, CoreArrayCellClass, CoreOps, CoreProperties;
CoreArrayCellClassImpl: CEDAR PROGRAM
IMPORTS CoreOps, CoreProperties
EXPORTS CoreArrayCellClass =
BEGIN OPEN Core, CoreArrayCellClass;
Start: PROC = {
CoreOps.RegisterCellClass[arrayCellClass];
arrayCellClass.properties ← CoreProperties.PutProp[on: arrayCellClass.properties, prop: CoreOps.printClassProcProp, value: NEW[CoreOps.PrintClassProc ← PropPrintArrayCellType]];
CoreOps.RegisterCellClass[mapCellClass];
mapCellClass.properties ← CoreProperties.PutProp[on: mapCellClass.properties, prop: CoreOps.printClassProcProp, value: NEW[CoreOps.PrintClassProc ← PropPrintMapCellType]];
};
Arrays
arrayCellClass: PUBLIC CellClass ← NEW[CellClassRec ← [name: "Array", recast: RecastArray, write: WriteArray, read: ReadArray]];
WriteArray: WriteProc = {
};
ReadArray: ReadProc = {
};
RecastArray: RecastProc = {
seqCell: SequenceCell ← NARROW[me.data];
recCell: CoreRecordCells.RecordCell ← NEW[CoreRecordCells.RecordCellRec];
new ← NEW[CellTypeRec ← [
name: me.name,
class: CoreRecordCells.recordCellClass,
publicWire: CoreOps.CopyWire[wire: me.publicWire],
data: recCell,
properties: CoreProperties.CopyProps[propList: me.properties]]];
recCell.internalWire ← NEW[WireRec ← [
structure: sequence]];
recCell.internalWire.elements ← NEW[WireSequenceRec[new.publicWire.elements.size + seqCell.stitches.length]];
FOR w: NAT IN [0..new.publicWire.elements.size) DO
recCell.internalWire.elements[w] ← new.publicWire.elements[w];
ENDLOOP;
FOR w: NAT IN [new.publicWire.elements.size..recCell.internalWire.elements.size) DO
recCell.internalWire.elements[w] ← NEW[WireRec ← [structure: sequence]];
recCell.internalWire.elements[w].elements ← NEW[WireSequenceRec[ seqCell.count]];
ENDLOOP;
FOR cell: NAT IN [0..seqCell.count) DO
newWire: Wire ← NEW[WireRec ← new.publicWire^];
newWire.elements ← NEW[WireSequenceRec[new.publicWire.elements.size] ← new.publicWire.elements^];
FOR seqWire:NAT IN [0..seqCell.length) DO
newWire.elements[seqCell.sequence[seqWire]] ← newWire.elements[seqCell.sequence[seqWire]].elements[cell];
ENDLOOP;
FOR stitchWire: NAT IN [0..seqCell.stitches.length) DO
internal: Wire;
IF cell < seqCell.count -1 THEN {
internal ← CoreOps.CopyWire[wire: seqCell.base.publicWire.elements[seqCell.stitches[stitchWire].source]];
recCell.internalWire.elements[stitchWire + new.publicWire.elements.size].elements[cell] ← internal;
newWire.elements[seqCell.stitches[stitchWire].source] ← internal;
};
IF cell > 0 THEN newWire.elements[seqCell.stitches[stitchWire].sink] ← recCell.internalWire.elements[stitchWire + new.publicWire.elements.size].elements[cell-1];
ENDLOOP;
recCell.instances ← CONS[NEW[CoreRecordCells.InstanceRec ← [
name: IF seqCell.base.name=NIL THEN NIL ELSE IO.PutFR["%g%g", IO.rope[seqCell.base.name], IO.int[cell]],
actualWire: newWire,
type: seqCell.base]],
recCell.instances];
ENDLOOP;
};
CreateArrayCellType: PUBLIC PROC [arrayCellType: ArrayCellType, name: ROPE ← NIL] RETURNS [cellType: CellType] = {
cellType ← NEW[CellTypeRec ← [
name: name,
class: sequenceCellClass,
publicWire: CoreOps.CopyWire[wire: args.base.publicWire],
data: args]];
FOR i:NAT IN [0..args.length) DO
wire: Wire ← cellType.publicWire.elements[args.sequence[i]];
newWire: Wire ← CoreOps.CreateSequenceWire[name: wire.name, base: wire, count: args.count];
cellType.publicWire.elements[args.sequence[i]] ← newWire;
ENDLOOP;
};
PropPrintArrayCellType: CoreOps.PrintClassProc = {
PrintArrayCellType[NARROW[data], out];
};
PrintArrayCellType: PUBLIC PROC [arrayCellType: ArrayCellType, out: STREAM] = {
IO.PutF[out, "\n\nBase cell type: %g", IO.rope[cell.base.name]];
IO.PutF[out, ", count: %g", IO.int[cell.count]];
IO.PutRope[out, "\nstitch wires:"];
FOR stitch: NAT IN [0..cell.stitches.length) DO
IO.PutF[out, " (%g, %g)", IO.rope[cell.base.publicWire.elements[cell.stitches[stitch].source].name], IO.rope[cell.base.publicWire.elements[cell.stitches[stitch].sink].name]];
ENDLOOP;
IO.PutRope[out, "\nsequence wires:"];
FOR seq: NAT IN [0..cell.length) DO
IO.PutF[out, " %g", IO.rope[cell.base.publicWire.elements[cell[seq]].name]];
ENDLOOP;
};
Maps
mapCellClass: PUBLIC CellClass ← NEW[CellClassRec ← [name: "Map", recast: RecastMap, write: WriteMap, read: ReadMap]];
WriteMap: WriteProc = {
};
ReadMap: ReadProc = {
};
RecastMap: RecastProc = {
};
CreateMapCellType: PUBLIC PROC [mapCellType: MapCellType, name: ROPE ← NIL] RETURNS [cellType: CellType] = {
};
PropPrintMapCellType: CoreOps.PrintClassProc = {
PrintMapCellType[NARROW[data], out];
};
PrintMapCellType: PUBLIC PROC [mapCellType: MapCellType, out: STREAM] = {
};
Start[];
END.