///CommonMBusSpecs.tiogaWrittenby:Sindhu,September1,19841:51:14pmPDTLastEditedby:Sindhu,March22,19859:17:20pmPSTLastEditedby:Barth,December13,19842:08:47pmPSTLastEditedby:McCreight,March22,19855:13:37pmPSTCOMMONMBUSSPECIFICATIONSTheCommonMBusDescriptionandSpecificationsDRAFTofMarch22,1985..nearlydone..Releaseas[Indigo]<Dragon>Documentation>CommonMBus>CommonMBusSpecs.tioga,.presscCopyright1985XeroxCorporation.Allrightsreserved.Abstract:ThismemoproposesacommonMbusforDragonandCworkstation.ItisintendedtobeusedbothasaconvenientsourceforinformationabouttheMbusandasareferencemanualforbusspecifications.ThememobeginswithabriefoverviewoftheMbus.Itthenlistsallthebussignalsanddefinesthemeaningofeachsignalgroup.Next,itusesthesesignalstodescribeindetailhowthebusoperatesatboththecycleandtransactionlevels,andhowcertaintransactionsareusedtomaintaincacheconsistency.Finally,itgivesthedetailedtimingofthebustransactionscurrentlydefined.XEROXXeroxCorporationPaloAltoResearchCenter3333CoyoteHillRoadPaloAlto,California94304ForInternalXeroxUseOnly���pï_,îâï]…îâîèî<î@î!Ýî#jî&°î+˜î-ãï[ÝîâîþîEî˜îœî"î$?î'…î,nî.¸ïZ6îâîþîEî˜îÉî#î%Tî(šî-ƒî/ÎïXîâîþîEî˜	îÁî$&î&cî)©î.’î0ÝqïVîâ�rîàïV�ïVî¼qîïV�ïVîè�rîÏïV�ïVîµ�qî(ïV�rïVîïsïMÏîâîšî Ï�î#ûtïHÙîâ
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��������TVm$é������������������������������COMMONMBUSSPECIFICATIONS2Contents1.Introduction2.BusSignals3.BusOperation4.BusTimingFORINTERNALXEROXUSEONLY���qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�zï^õîâ{ï[§î¤î0ïXXî¤î0îòïU	î¤î0îòïQ»î¤î0îòrïî Ùî#­î*$î.Ÿî1G��������k��������TVm$�_��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS31.IntroductionTheMbusisahighbandwidthsynchronousbusthatinterconnectsamultiprocessorsystem.FivekindsofdevicesconnecttoanMbus:caches,thatintermediatebetweenprocessorsandthebus,memories,someofwhichmaybemultiported,I/Odevicecontrollers,amap,responsibleforinformingthecachesaboutthecurrentvirtual-to-physicalmemoryaddressmapping,anarbiter,thatassignsmastershiptoatmostonerequestingdevice.ThisdocumentisthespecificationfortheMbusinterfaceofcaches.ItimpliesrestrictionsonotherdevicesthatconnecttotheMbusaswell,butitisnotintendedtospecifythosedeviceswithanycompleteness.MbuseshaveabriefbutinterestinghistorywithinXerox.Thecacheconsistencyprotocol,whichmanyconsidertobethekeyideathattheMbusimplements,firstoccurredtoDashiellofXeroxEDandThackerofXeroxPARCabout1980.TheoriginalintentionwasthatEDandPARCdevelopacompatibleMbusthatcouldbeusedbyPARC'sworkstationprojectsandED'sprinterprojects.Notenoughenergywasdevotedtoovercomingtheincreaseofentropy,andbysummerof1984EDnearlyhadaworkingMbusandPARChadapaperdesignofaratherdifferentMbus.SincethenithasbecomeclearthattheEDMbusasitexiststoday(weshallcallthattheESSMbus)willnotsatisfyallofED'srequirementsforitsplannedCworkstationline,andsoconsiderableeffortisbeingdevotedatEDandPARCtosettlingonacommondesignforthesecond-generationMbus.ThisdocumentisthefirstdetailedproposalfromPARCinthatdirection.ManyoftheapparentlyarbitrarychoicesinthefollowingsectionsaredictatedbyastrongdesirethatexistingESScachesfunctionaswellaspossibleonthenewcommonMbus.Theremainderofthedocumentgoesintogreaterdetailaboutthestructure,operation,andtimingoftheMbus.Thenextsectionliststhebussignalsindetailandgivesthemeaningofeachsignal.Section3nextusesthesesignaldefinitionstoexplainhowthebusoperates:itdiscussesarbitration,liststhesetofbuscommandscurrentlydefined,showshowthesecommandsareusedineachofthepossibletransactions,showshowtransactionsareusedtomaintaincacheconsistency,andintroduceshousekeepingoperationstodealwithaddressspaceswitchesandmultiportmemories.Finally,Section4discussesthetimingofarbitrationandofeachtransactionindetail.2.BusSignalsAnMbusconsistsofthreeindependentgroupsoflines.Thefirstistheclockinggroup.Thesecond,calledthearbitrationgroup,assignsbusmastership.Thethird,calledthetransfergroup,transportsdataoncemastershiphasbeenestablished.Thefollowingdescriptionusesthesenamingconventions:S[a..b)denotesagroupof(b-a)linesthatencodethebitsrepresentingthesignalS;mostsignificantbitsofthesignalarewrittenleftmost,andhavethesmallestnumericindex.Asignalrepresentedbyasinglewireiswrittenunencumberedwiththe[)notation.Allsignalsareassumedtofollowpositivelogicunlesstheyhavean"n"asthesecondFORINTERNALXEROXUSEONLY��qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�zï^õîâî¾qï[¦î¤î�îbî~îo�îî!Ëî),
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b��������TVm$Â������������������������COMMONMBUSSPECIFICATIONS4characterofthesignalname.Someoftheselineshavepullupresistorstoensurethattheyremainunassertedduringcycleswhentheyarenotdriven.Theseresistorsdonotsupplyenoughcurrenttode-assertalineinonecycle;howevertheymustde-assertthelineinaminimumresetperiod.2.1ClockingGroupTheMbusistimedincyclesofatwo-phaseclock.ThephasesarenamedAandB,andaclockcyclebeginsattheleadingedgeofAandendsatthetrailingedgeofthefollowingB.AsignalthatconformstostandardMbustimingisdrivenontotheMbusassoonaspossibleafterthestartofphaseA,andissensedfromtheMbusbylatchesthatareopen(enabled)duringphaseB.ThismeansthatthelargestportionofaclockcycleisavailablefordatatopropagateandstabilizeontheMbus.AllofthefollowingsignalsexceptMPhAandMPhBconformtostandardMbustiming.MPhAThisisassertedduringthe"first"phaseofatwo-phaseclockcycle.MPhBThisisassertedduringthe"second"phaseofatwo-phaseclockcycle.MHoldThestateofthislineassampledattheendofcycleidetermineswhetherthestateoftheMbussystemattheendofcyclei+2istobeidenticaltoitsstateattheendofcyclei+1.MnResetThislineisheldassertedduringpower-up,andisassertedforatleast128consecutivecycleswheneveritisasserted.ThecyclefollowingthecycleinwhichMnResetisde-assertedisavalidMbuscycle.2.2ArbitrationGroupThearbitrationgroupconsistsofapairofrequest/grantlinesforeachbusrequestor,andoneothersharedlinecalledMnNewRQ.Asingle,centralarbitertime-multiplexesthetransfergroupamongseveralcontendingdevices.Eachofthesedevicesmakesrequeststothearbiterusingitsdedicatedrequestline,andthearbitergrantsmastershipofthebususingthededicatedgrantlines.Adevicethathasbeengrantedthebusiscalledbusmaster.Thesequenceofcyclesinitiatedbyamasterwilltypicallyinvolveatleastoneotherdeviceonthebus;suchadeviceiscalledaslave.MnRq[0..16)FORINTERNALXEROXUSEONLY���qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�qï_/îâîËî„îãîÎï\³î¤îuî*î°îçî!)î%Œî*Ôî,~î0àî3ªî6¶î;Y	ï[îâîî¿î®îøî!†î$5î)Õî.î3˜î5Ùî8ˆî=4ïYeîâîÂî‡îN�îî\î! î#ãî'æî-€î0¦î4%î9ìî<bî?/î@ô�ïW½îâî7î~{ïTnîâîîäqïQî¤î‡�îmîî‡îî 9î$;î&��î'6î-Äî2Kî5/î9 î;ÿî@‘�ïOwîâî°îŒîZ�î›îFîÐî#6î$æî']î,Gî/¥î1u�î3î5çî9:î:êî=aïMÏîâîîÎî$î-îa�îäî#Æî&Šî,‰î.-î3¿�î5î8î<mî=ÏïL(îâî%î—�î„î-îîîGî î%\î(ªî+î.?î0î3ÿî5öî8Àî:?î>·ïJîâîB�îîµî²î:î	î!^î$Ñî*òî/cî3Fî5î8ªî<ïî?¾ïHÙîâî/î�î¬�îÈîNî!´î#î(Àî*ðî-çî/ˆî5Üî8†î=Æî?¾ïG2îâ�îÂîAîšîZîÀî Øî%Nî)¥î.&î0ãî5Dî:Îî<ƒïE‹îâ�î¼îSpïB;îâqï>ìî¤î¾î)îaîÑî"1î&jî*Kî,�î-.î3°î7Dpï;œîâqï8Lî¤î¾î)îaîÑî"1î(#î,î-¾�î.èî5jî8þpï4ýîâqï1­î¤î‰îÈîî>îî ¾î&:î'àî*Mî-î.Ùî2Z�î3O	î:cî?¾ï0îâî$îîî_�îJîòî~î!(î#˜î&aî(+î+¯î.¹î06î1õî3÷î9˜î;Xî=Cî@…ï._îâîAîùî²î%pï+îâqï'¿î¤îùîëî’îèî"Zî'î-Ïî0Âî2iî7Ûî:Tî<(î?ˆï&îâ
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rïî Ùî#­î*$î.Ÿî1Gÿ�������Ó��������TVm$•COMMONMBUSSPECIFICATIONS5Theselinesareusedbythecachestorequestbusmastership.Thereisadedicatedlinefromeachcachetothebusarbiter.MnGnt[0..16)TheselinesareusedbythearbitertosignalwhichofthecachesisthenextMbusgrantee.Liketherequestlines,theselinesarealsodedicated,onepercache.Thereisapossibilitythattheywillbereplacedby4encodedgrantlinesthatsupplythenumberofthecachetowhichthebushasbeengranted.Alternatively,theseencodedlinesmayberuninadditiontothedecodedlines.TheencodedlinesareneededbytheMapprocessortofigureoutwhichprocessoriscurrentlybusmaster.MnNewRqThislineislogicallyunnecessary,butcanreducethevarianceinMbuslatency.Thislinesignalsthatthecurrentgranteewantstoretainhisgrant,butiswillingtorelinquishitifthereareotherrequestersatthistime.Thislinehasapullupresistor.2.3TransportGroupThetransfergroupconsistsofapproximately42wires.MnAdCycleThislineisassertedlowduringcycleswhenavalidcommandisbeingassertedonMCmd.Thislinemaybeassertedeitherbythemasterofthecurrenttransactionorbytheslaveselectedbythefirstcycleofthecurrenttransaction.MTransport[0..36)Thesethirty-sixwiresareusedtoencodethreefields:MCmd[0..4),MAddr[0..32),andMData[0..32).Sincethisaddsuptomorethanthirty-sixwires,thesefieldsaretime-multiplexed.ThesomewhatpeculiarwayinwhichthismultiplexingisdoneallowstheESScachetoattachtothirty-twoofthem,MTransport[5..36).MCmd[0..4)=MTransport[4..8)ThisfieldisonlyvalidifMnAdCycleisasserted.ItencodestheMbuscommand,whichspecifiestheactionduringthecurrentbuscycle,andmaycarryimplicationsforfuturecyclesaswell(seetransactions,section3.3).ItisassertedbythesamedevicethatisassertingMnAdCycle.ThecommandscurrentlydefinedarediscussedlaterinSection3.2.MAddr[0..32)=MTransport[0..4)|MTransport[8..36)ThisfieldisonlyvalidifMnAdCycleisasserted.ItsinterpretationdependsonMCmd,whichisadisjointfield.Thisfieldnormallycarriesanaddress.MData[0..32)=MTransport[4..36)ThisfieldisonlyvalidifMnAdCycleisde-asserted.ItsinterpretationdependsonpreviousvaluesofMCmd.Thisfieldnormallycarriesdata.FORINTERNALXEROXUSEONLY��qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�qï_/î¤îçîcî÷îuî!±î$Rî(ãî*Óî/éî2À
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Aîâîèîwî¥î^î"î%î(Mî.î2wrïî Ùî#­î*$î.Ÿî1Gÿ�������È��������TVm$m������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS6MParityThislinecarriestheparityofMTransport.TheparityisoddanddrivenonecyclelaterbythedevicethatdroveMTransport.MnSharedThislineindicatesthatacopyoftheaddressedmemorywordispresentinaslavecache.Thislinehasapullupresistor.MnAbortThislinepreventsmemoryfromrespondingtoaReadQuadandallowsacachetorespondinstead.Thiswireisnotlogicallynecessarytothecacheconsistencyprotocol,butitallowsaperformanceoptimization.Thislinehasapullupresistor.MnHousekeepingInProgressFollowinganycycleinwhichthislineisnotasserted,everycachethatisdoinghousekeepingassertsit.Followinganycycleinwhichitisasserted,everycacheactivelyde-assertsit.Twounassertedcyclesinsuccessionmeanthatnohousekeepingisinprogress.Thislinehasapullupresistor.MnErrorThislineisusedtosignalabuserror.Theonlybuserrorcurrentlydefinedisbusparityerror.Thislinehasapullupresistor.3.BusOperationMbusoperationisspecifiedattwolevels:cyclesandtransactions.Asexplainedearlier,acycleisonecompleteperiodofthesystem-widetwo-phaseclock.Atransactionisasequenceofcontiguouscyclesinitiatedbysomebusmaster.Duringthefirstcycleofeverytransaction,MnAdCycleisasserted,MCmdspecifiesthetransactiontype,andMAddrspecifiesanaddress,whoseinterpretationvarieswithtransactiontype.Subsequentcyclestransferdata,performothermanipulations,orsignaltheendofthetransaction.Recallthatthedevicethatinitiatesatransactioniscalledthebusmaster,andotherdeviceswithwhichitinteractsarecalledslaves.Busmastershipisgrantedbythearbiter.Thusoverallbusoperationisasimplepipelinedcyclicprocessofarbitrationfollowedbytransactionexecution.Thedescriptionbelowfirsttakesuparbitration.ItthendescribesthevariousMbuscommandsaswellasthesetoftransactionsthatusethesecommands.Forcompleteness,italsodiscusseshowcachesmaintainconsistencyofmultiplecopiesofshareddata.Finallyitdiscussesasetofhousekeepingoperationsthatdealwiththemappingproblemsintroducedbymovingaprocessorfromoneaddressspacetoanother,andwiththeconsistencyproblemsintroducedbymultiportmemories.ThedetailedtimingofarbitrationandofeachofthetransactionsisnottakenupherebutislefttoSection4.3.1ArbitrationFORINTERNALXEROXUSEONLY��qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�pï_:îâqï[ëî¤îÐî˜îîvî"€î$K
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rïî Ùî#­î*$î.Ÿî1G�������*��������TVm$’��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS7ThesignalsinvolvedinarbitrationaretheMnRq-MnGntpairsrunningtoandfromeachpotentialmasterandthearbiter,andasinglelineMnNewRqusedtoincreasethefairnessofarbitration.Adevicerequeststhebusbyassertingitsrequestline.IfoneormoreMnRqlinesareasserted,andthereisnomaster(grantee)atthemoment,thearbiterperformsagrantcycleinwhichitissuesthebusbyassertingMnGntforadevicethathasMnRqasserted.ThebusmasterkeepsMnRqassertedwhileitstillwantsthebus,andthearbiterinturnkeepsthatmaster'sMnGntasserted.Ifthemasterisexecutingalongsequenceofcyclesthatisnotrequiredtobeatomicwithrespecttootherdevices,itmayassertMnNewRqtoindicateitswillingnesstogiveupthebusifthereareotherrequestspending(forcorrectoperation,MnNewRqmustbeassertedonlybythecurrentmaster).MnNewRqcausesthearbitertodoagrantcycleeventhoughthecurrentmasterstillhasMnRqasserted.Thisstrategypreventsamasterfromhoggingthebus(unless,foratomicity,itneedsto).Atthesametime,itavoidswastingcyclesinthecasethatnodevicesarewaitingtogetthebus.Asolutioninwhichthemasterreleasesandreacquiresthebus,forexample,doeswastecyclesinthiscase.3.2MBusTransactionsTherearecurrentlyninemastertransactions:ReadQuad,WriteQuad,WriteSingle,MapRef,MapRefDirty,IORead,IOWrite,IOReadFlow,andIOWriteFlow.Thebusmasterinitiatesamastertransactionbyassertingtheappropriatecommandwithanaddressofsomekind.ThiscommandandaddressisinterpretedbyeverydeviceattachedtotheMbus,andoneormoredevicesdecidetoactasslavesduringtheremainderofthetransaction.Somemastertransactionsconsistofafixedsequenceofcycles:WriteSingle,IORead,andIOWrite.Othersareflow-controlledbytheMnDVline:ReadQuadandWriteQuad.Theremainderareflow-controlledbytheslavetransactionDone.Flow-controlledmastertransactionsbeginwithafixedsequenceofcycles,dependingonthetransaction,waitfortheirflow-controllingevent,andthenterminateinafixedsequenceofcycles,againdependingonthetransaction.Flow-controlledtransactionsmustselectexactlyoneslave.TheMbusspecificationincludesmeansfordetectingwhenthisisnotso.(Ohyeah?Howdowedothis?WhateveriseasiestforEDshouldprobablyprevail.)Transactionsthatareflow-controlledbyDonemaycontainsubtransactionsthatarenotflow-controlledbyDone.Duringthosesubtransactions,theslaveofthemaintransactionactsasmasterofthesubtransaction.IOdevicesmayrespondtoanyorallofthefourIOtransactions.MbuscommandsarecarriedintheMCmdfieldandarevalidwhenMnAdCycleisasserted.Twelveofthesearecurrentlydefined,andtheotherfourarereservedforfutureuse.Inthedescriptionbelow,thedecimalnumberincurlybracketsafterthecommandnameindicatestheencodingofthecommand.(Onpage8ofthe21Jan84ESScachespecification,thereare(optional?)waitcyclesappearingbeforeseveraltransactions.Whatdoesthismean?)ReadQuad{0or2(sigh!)}ThiscommandisissuedbythemasterduringthefirstcycleofaReadQuadtransaction,whichreadsaquadintothemasterfrommemoryorfromanothercache.FORINTERNALXEROXUSEONLY���qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�qï_/î¤î~îïî‹î ;
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×îâîîî˜�î©î"î$Îî'î+lî.ºî4î5ºî9î=úrïî Ùî#­î*$î.Ÿî1G���������������TVm$Ú����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS8Aquadisfourcontiguous32-bitwordsalignedinphysicaladdressspacesuchthattheaddressofthefirstwordis0MOD4.DuringthisfirstcycleMAddristhephysicaladdressofoneofthewordsinthequad.ThetransactionthenconsistsofzeroormorewaitcyclesuntiltheMnDVlinesignalsthatthememorysystemisresponding.TheaddressedwordwillbeassertedonMDatabytheslaveduringthatcycle.TheremainingwordsofthequadwillbeassertedonMDatabytheslaveinsubsequentcyclesinanorderdeterminedbytheiraddressMOD4:AddrTransportorder0=>{0,1,2,3}1=>{1,0,3,2}2=>{2,3,0,1}3=>{3,2,1,0}Cachesbuilttothisspecificationwillunderstandboth0and2asencodesforReadQuad,butwillissueonly0.WriteQuad{1or3((sigh!)}ThiscommandisissuedbythemasterduringthefirstcycleofaWriteQuadtransaction,whichwritesaquadfromthemastertomemoryandtoothercaches.InthefirstcycleMAddrcarriestheaddressofthequadwhich,unliketheaddressforaReadQuadtransaction,mustbe0MOD4.InsubsequentcyclesthemasterassertsthedataofthequadonMData,inorderofincreasingaddress.ThemasterreleasesMnRqforthistransactioninthecycleafterMnDVisassertedbytheslave.Cachesbuilttothisspecificationwillunderstandboth1and3asencodesforWriteQuad,butwillissueonly1.WriteSingle{7}ThiscommandisusedbythemasterduringthefirstcycleofaWriteSingletransaction,whichwritesasinglewordintothephysicaladdressspace.WriteSingleneverwritesthewordtomemory,butonlytocachesthatalreadyholdacopyofthequadcontainingthewordbeingwritten.MAddrcarriesthephysicaladdressofthewordinthefirstcycleofthetransaction.Thedataisassertedbythemasterinthenextcycleofthetransaction.MapRef{12}Thiscommandisusedbythemasterduringthefirstcycleofavirtual-to-physicalpagetranslationtransaction.Useofthistransactionindicatesthatthemasterintendstoreaddatainthereferencedpageofitsvirtualaddressspace(eachmastermaybeoperatinginadifferentvirtualaddressspace).InthatfirstcycleMAddr[7..32)containsavirtual512-byte-pagenumber.Thefinalcycleofthetransactionisthecycleinwhichtheslave(map)assertsaDonecommandthatcontainstheresultsofthetranslationinMAddr.(DoestheESScachereallyrequirethreedeadcyclesaftertheDone?Isthatbecauseitsmatcheristiedup?)FORINTERNALXEROXUSEONLY��qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�qï_/îâ�pîyï_/�ï_/î*qï_/îÖîLî[	îWî#Yî'pî,Nî.î3_î8Tî<î?Pï]ˆîâînî…îkîøîýî!²î#K�rî$¬ï]ˆ�ï]ˆî%¾qï]ˆî(1î*›î/‘î2_î5dî9î>&î?¾ï[àîâî/îîÒî~î7î!—î%£î'Qî)±ïYeî¤îƒ
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î3ñî6±î9íî<“î>ˆïuîâî î^îyîõî3îVî‹ïî Ùî#­î*$î.Ÿî1G�������*��������TVm$#��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS9MapRefDirty{10}Thiscommandisusedbythemasterduringthefirstcycleofavirtual-to-physicalpagetranslationtransaction.Useofthistransactionindicatesthatthemasterintendstowritedatainthereferencedpageofitsvirtualaddressspace(eachmastermaybeoperatinginadifferentvirtualaddressspace).InthatfirstcycleMAddr[7..32)containsavirtual512-byte-pagenumber.Thefinalcycleofthetransactionisthecycleinwhichtheslave(map)assertsaDonecommandthatcontainstheresultsofthetranslationinMAddr.IORead{4}ThiscommandisusedbyamasterduringthefirstcycleofanIOReadtransaction.MAddrcontainstheIOregisteraddress.Thesecondandthirdcyclesareidle.AnynumberofdevicesmaygeneratesideeffectsinresponsetoanIORead,butexactlyoneslavemustassertdataonMDataduringthefourthcycle.TheinterpretationofanIOReadisentirelyuptotherespondingdevice.Thusitmayactuallyreadfromarealdeviceormaycausesomesideeffect,orboth.IOWrite{5}ThiscommandisusedbyamasterduringthefirstcycleofanIOWritetransaction.MAddrcontainstheIOregisteraddress.ThemasterassertsthedataonMDatainthenextcycle.Anynumberofslavesmayrespond,buttheydosoundetectedbytheIOWriteprotocol.IOReadFlow{8}ThiscommandisusedbyamasterduringthefirstcycleofanIOReadFlowtransaction.MAddrcontainstheIOregisteraddress.TheslavesignifiesreadinessbyaDonecommand,andassertsdataonMDatainthefollowingcycle.IOWriteFlow{9}ThiscommandisusedbyamasterduringthefirstcycleofanIOWriteFlowtransaction.MAddrcontainstheIOaddress.DuringthesecondcyclethemasterassertsdataonMData.InsomesubsequentcycletheslavesignifiesreadinessbyaDonecommand,andthemasterre-assertsthesamedataonMDatainthefollowingcycle.Done{14}Thiscommandisissuedbytheslavedevicetoflow-controlaMapRef,MapRefDirty,IOReadFlow,orIOWriteFlowtransaction.ThevaluethatitassertsonMAddrdependsonthetransactionandtheslave.IfthetransactionisMapReforMapRefDirty,thentheslaveisthemap.MAddr[0..25)containsthenumberofthe512-bytephysicalpagecorrespondingtothevirtualpagethatinitiatedthetransaction.MAddr[25..28)carriesoneofthefollowingorders:NoClear{7}--noactionrequiredFORINTERNALXEROXUSEONLY��qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�pï_,îâ
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Òî¤î6îËîBîIî!arïî Ùî#­î*$î.Ÿî1G�������ê��������TVm$—��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS10ClearRPDirty{6}--writepermissionforthecurrentphysicalpageissummarilycancelledinallcaches.Fromthispointon,anycachewishingtowritetoavirtualaddresslyinginthisphysicalpagemustacquirenewpermissionviaMapRefDirty.ClearVPValid{4}--virtualmappingstothecurrentphysicalpagearesummarilycancelledinallcaches.Fromthispointon,anycachewishingtoreferencethisphysicalpagemustacquireanewvirtual-physicallinkageviaMapReforMapRefDirty.WriteProtectFault{2}--aMapRefDirtyfailedtoacquirewritepermissionfromtheslave.ThisorderisofinterestonlytotheMbusmaster.PageFault{1}--theslavefailedtolocateavalidvirtual-to-physicalmapping.ThisorderisofinterestonlytotheMbusmaster.MAddr[28..32)carriesagroupoffourflagsfromwhichthemastercacheshouldupdateitsmappinginformation(exceptifthereisaPageFault):MAddr[28]--reservedMAddr[29]--writeprotect(=NOTdirty)MAddr[30]--dirtyMAddr[31]--referenced(=true)(Note:Theseflagsareallredundant.Theycanbeinferredfromthetransactionanditsfaults.TheyareincludedforbackwardscompatabilitywiththeESScache.)IfthetransactionisIOReadFloworIOWriteFlow,andtheslaveisnaive(ignorantofmapping),duringtheDonecyclethefieldMAddr[25..28)carriestheorderNoClear.IOdataisthentransportedinthefollowingMbuscycle.IfthetransactionisIOReadFloworIOWriteFlow,andtheslaveissophisticated(awareofmapping,probablythemapitself),thenMAddr[0..25)cancontainthenumberofa512-bytephysicalpage,andMAddr[25..28)cancontaintheordersNoClear,ClearRPDirty,orClearVPValid.IOdataisthentransportedinthefollowingMbuscycle(eventhoughthatdatamaybemeaningless;theIOReadFloworIOWriteFlowmayhavebeenexecutedforthesideeffectsofitsDonecommand).Infact,themapwillprobablycontaina"Donereflector"IOregister,thatwillsimplysavethedatasentbythemasterinanIOWriteFlowtransactionandretransmititintheappropriatefieldsoftheDonecommandthatterminatesthetransaction.Reserved{6,11,13,15}Thesecommandsarereservedforfutureuse.Cachesbuilttothisspecificationwillignorethem.3.3TheCacheConsistencyProtocolThecacheconsistencyproblemistopreventmultiplecopiesofadatumindistinctcachesfromhavingdifferentvalues.ThisproblemarisesbecauseDragoncachescontainshareddatathatmaybewritteninto.ThesolutioninvolvestheuseoftheMnSharedandMnAbortbuslinesandtwoadditionalbitssharedandownerstoredwitheachquadinacache.ForagivenFORINTERNALXEROXUSEONLY���qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîEqï_'î¤îDîÅî(î!’	î(mî*–î,âî1—î6Ðî:î;Zï]îâîãî”î†î·î!î$3î'Õî*6î,Ùî0¨î5µî7fî:æî<—�î=Ãï[ØîâîÌî>îìîî Ûî$!î'Šî,iî/W	î6Gî8„ïY]î¤î7î¬îî"=î(]î)ëî,*î0Ôî6î9'î;ZïWµîâî	îàîùîvî"tî%>î)î+î.Wî2Lî7î9Vî?|ïVîâîÕîÁîÎî"R�î$!î'µî1÷î7dî:Fî@ZïTgîâïQìî¤îÆîIî ­�î!Ä
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Íî#®î'÷î+7î.Žî23î4�î5Vî:Iî=�î>jrïî Ùî#­î*$î.Ÿî1G�������á��������TVm$ï������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS11quad,ifsharedisfalsethennoothercachecontainsacopyofthequad.However,ifsharedistrueothercachesmayormaynotcontainthequad(thereisuncertaintybecausewhensharingstopsthisfactisnotdiscoveredimmediately).Owneristrueifandonlyifthelastwriteintothequadwasintothisverycache.AcacheinitiatesaReadQuadwhenitgetsamiss;itissuesaWriteQuadwhenaquadneedstoberemovedfromthecachetomakeroomforanotherquad(onlyquadswithownersetneedtobewrittenbacktomemory);anditissuesaWriteSingleandsetsownerwhenitsprocessordoesawritetoaquadthathassharedset.WhenacacheissuesaReadQuad,WriteQuad,orWriteSingleallothercachesonthebusmatchthequadaddresstodetermineiftheyholdacopyofthequad.AnycachethatmatchesassertsMnSharedtosignalthatthequadisshared.DuringReadQuadsthemasterandallmatchingslavescopythevalueofMnSharedintothesharedbitforthatquad.Also,whenacacheissuesaWriteSinglethemastercopiesthevalueofMnSharedintothesharedbit.Thisensuresthatsharingisdetectedassoonasitstartsandiseventuallydetectedwhenitstops.DuringReadQuad,WriteQuad,orWriteSingle,allmatchingquadsexcepttheonesupplyingdatatothebusloadnewvaluesfromthebusandcleartheirownerbits.Theownerbitisseteachtimeaprocessorwritesoneofthewordsofthequad.Ifthequadisshared,theresultingWriteSinglewillupdateallothercopiesofthequadandcausetheirownerbitstobecleared.Thusatanytimeatmostoneofthecacheswillhaveownerset.Ownermaynotbesetatall,ofcourse,ifthequadhasnotbeenwrittenintosinceitwasreadfrommemory.DuringaReadQuad,iftheownerbitissetonamatchingquad,thatcacheassertsMnAbortandsuppliesthedatatotheMbusitself(sincethememorydoesn'tknowthecurrentvalue).OtherwiseMnAbortisnotsetandthememorysuppliesthedata.3.4HousekeepingoperationsWeareleftwithtwoproblemsthatDragonsandprobablyCmachineswillhavetodealwith,andthatthatthebasicMbusoperationsabovehavedealtwithincompletely.Thefirstiscontextswitchesbetweenaddressspaces.Whenaprocessormovesfromoneaddressspacetoanother,alloftheoldvirtual-to-physicalassociationsinitscachesthatarenotalsopresentinthenewaddressspacemustbebroken.TherearetwowaystosolvethisproblemwiththebasicMbusoperations.First,theprocessorcanissueasequenceofPbusreferencesthatvictimizesalldatainallitscaches.Second,asequenceofMbusDonecommandscanbegenerated,incooperationwithasophisticatedslave,toclearVPValidinallcachesforallphysicalpagesthatmightbeknowntotheprocessor.Bothofthesesolutionsaresoexpensiveastoprohibitfrequentcontextswitchesbetweenaddressspaces.Thesecondremainingproblemismultiportmemories.Somememorieshavetwoports,aprimaryonewhichattachestotheMbusandasecondaryonewhichdoesnot.SuchamemorymightappearinadisplaycontrollerthatcandoautonomousBitBlt,forinstance.Whenbothportsareactive,ourprotocolformaintainingconsistencydoesnotwork,becausethesecondaryportcandoreadsandwriteswithoutinformingtheMbus.Apartialsolutiontothesecondproblemistotime-multiplextwo-portmemoriesamongseveralaccess-limitedstates.AtanymomentsuchamemoryisinoneofFORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîEqï_/îâî·îîzîäîî 7î";î%Ùî)£î/�î0-î3}î54î7’î;éï]ˆîâî<îšîÿîÜîtî ½î#ºî%wî(tî*âî/ºî2î5Šî9†î:ê
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î!î%Íî'åî*¢î0,î3z�î4Àî:Jî;Òî=î@erïî Ùî#­î*$î.Ÿî1Gÿ�������R��������TVm$g����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS12threestates:eitheritssecondaryportisentirelyinactive,orelsetheMbushasnoknowledgeofit,orelsebothMbusandsecondaryportarepreventedfromwriting.Thissolutionisabittoocoarse.Wecanrefineitbyallowingeachpageinsuchamemorytobeinoneofthethreestatesindependentofthestatesofotherpages.TodealwiththefirstproblemweintroduceanoperationcalledDeMapping(breakingvirtual-to-realassociation,leavingorphansinthecache).TodealwiththesecondweintroduceLaundering(rewritingalldirtyquadstomemoryandleavingthemclean)andFlushing(clearingRPValid).(FlushingappearsnottobenecessaryifReadQuadsalwaysrefillcleanorphansfrommemory.LaunderingandDeMappingsufficeinthatcase.)Collectivelywerefertotheseashousekeepingoperations.Forefficiencyhousekeepingoperationsapplynottosinglephysicalpagesbutrathertosetsofphysicalpagesmatchingamaskof{0,1,don'tcare}"trits".Housekeepingoperationscanbeappliedtoallcachesatthesametime,ortoasinglecache.Eachcachecontainsapairof32-bitregistersthattogetherholdthephysicalpagemasktobeused.Inaddition,eachcachehasasinglehousekeepinginitiationregisterlocatedattwoI/Oaddresses:abroadcastaddress,andaprivateone.1bitsstoredintoappropriatebitsoftheinitiationregistercauseinitiationofDeMap,Launder,andFlush.(IfwecoulduseaddressesinESScachemailboxspace,therewouldbeawayofnotifyingprocessorsattachedtoESScachesthatthesehousekeepingoperationswerebeinginitiated.)ThisallimpliesthatacacheneedstorespondasaslavetoitsownIOWrites,andprobablytoitsownIOReadsaswell.Itisnotnecessaryforcachestorespondtoflow-controlledIO.LaundercanrequireenoughMbuscyclestotransportalldirtyquadsineverycachebacktomemory.WhileaLaundryoperationisunderwayeachcachere-arbitratesfortheMbusforeverydirtyquadthatitownsandneedstostore.RequestsfromthePbussidedemandingMbusservicehavehigherprioritythantheoperationrequests.Thesestipulationstogetherpreventahiccupfromoccuringinthesystemwhenthereisagreatdealofdirtydatatobelaundered.NotonlyLaundry,butallhousekeepingoperations,dependingontheirimplementations,maytakemanycyclestocomplete.Conceptuallyeachcachemaintainsahousekeepinginprogressbitthatindicatesthatahousekeepingoperationhasbeenstartedinthatcachebutnotyetfinished.WhetheranoperationisinprogressinanycacheinthesystemcanbeknownbyobservingthestateoftheMnHousekeepingInProgresswirefortwosuccessivecycles.Ifitisnotassertedinsomecyclei,thenanycachewithanoperationstillinprogresswillassertMnHousekeepingInProgressincyclei+1.Ifitisassertedincyclei,theneverycachewillde-assertitincyclei+1.MnHousekeepingInProgresswillthustoggleonandoffuntileverycachehasfinishedthelasthousekeepingoperation.EachcachehasameansbywhichMHousekeepingInProgress[i+1]ORMHousekeepingInProgress[i]maybereadfromitsPBuswithoutneedingMbuscycles.Thealertreaderhasalreadynoticedthatconcurrenthousekeepingoperationscouldbeanightmare.Weavoidconcurrencybymaintaining,asasoftwareconvention,aglobalhousekeepinglockinshared(andalwaysmapped)memory.Todohousekeepingaprocessmustacquirethelock,verifythatprevioushousekeepingisfinished,initiatetheoperation,and(iflogicallynecessary)holdthelockuntilhousekeepingisonceagainfinished.FORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîEqï_/îâîwî²î«î’î#
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îâîOïmrïî Ùî#­î*$î.Ÿî1Gÿ�������	��������TVm$vCOMMONMBUSSPECIFICATIONS144.3WriteQuadFigure4showsthetimingforWriteQuad.Cycles0through1aredevotedtoarbitrationasusual.Duringcycle2themastersetsMCmdtoWriteQuad,MAddrtotheaddressandassertsMnAdCycle.Duringcycle3themasterdrivesthefirstdatawordontoMDataanddeassertsMnAdCycle.Duringcycle4themasterdrivestheseconddatawordontoMDataandiftherearezerowaitstates(w=0)thememoryassertsMnDV.Duringcycle5themastersendsthethirddatawordonMDataandiftherearezerowaitstates,deassertsMnRq.ThememorydeassertsMnDViftherearezerowaitstates,orassertsMnDVifthereisonewaitstate.Incycle6themasterdrivesthefourthwordontoMData,anddeassertsMnRqifthereisonewaitstate.IftherearezerowaitstatesthearbiterdeassertsMnGnt.ThememorydeassertsMnDVifthereisonewaitstate,orassertsMnDViftherearetwowaitstates.Incycle7,iftherearetwowaitstates,themasterdeassertsMnRqandthememorydeassertsMnDV.IfthereisonewaitstatethearbiterdeassertsMnGnt.IftherearethreewaitstatesthememoryassertsMnDV.Finally,thereareanarbitrarynumberofwaitcycleswhichareterminatedbythememoryassertingMnDV,followedinthenextcyclebythemasterdeassertingMnRq,andinthenextcyclethearbiterdeassertingMnGnt.NotethattheminumumnumberofcyclesforWriteQuadis5.4.4WriteSingleFigure5showsthetimingforWriteSingle.Cycles0through1aredevotedtoarbitration.Duringcycle2themasterdeassertsMnRq,setsMCmdtoWriteSingle,setsMnAdrtotheaddress,andassertsMnAdCycle.Duringcycle3themastersetsMDatatothedataanddeassertsMnAdCycle.ThearbiterdeassertsMnGnt.Duringcycle4anymatchingslaveassertsMnShared.Duringcycle5anymatchingslavesdeassertMnShared.4.5IOReadFigure6showsthetimingforIORead.Arbitrationtakesplaceduringcycles0through1.Duringcycle2themasterassertsMnAdCycle,assertsIOReadonMCmd,assertstheIOregisteraddressonMAddr,anddeassertsMnRq.Duringcycle3,themasterdeassertsMnAdCycle,andthesingleslaveassertsdataonMData.4.6IOWriteFigure7showsthetimingforIOWrite.Cycles0through1areforarbitrationasusual.Duringcycle2themasterassertsMnAdCycle,assertsIOWriteonMCmd,assertstheIOregisteraddressonMAddr,anddeassertsMnRq.Duringcycle3,themasterassertsthewritedataontoMDataanddeassertsMnAdCycle.4.7IOReadFlowFORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE{ï_,îâîqï\±î¤î�î^îvîàî"Eî$Ž	î,§î1�î2Lî7�î8Îî;-î@oï[	îâ
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Òîâî	rïî Ùî#­î*$î.Ÿî1G�������4��������TVm$Ù������������������������COMMONMBUSSPECIFICATIONS15Figure8showsthetimingforIOReadFlow.Cycles0through1areforarbitrationasusual.Duringcycle2themasterassertsMnAdCycle,assertsIOReadFlowonMCmd,assertstheIOregisteraddressonMAddr.Duringcycle3themasterdeassertsMnAdCycle.Followingcycle3therecanbew>0waitcycles,duringwhichtheslavedoesnotassertMnAdCycleandMCmd=Doneduringthesamecycle.Duringcycle4+wtheslaveassertsMnAdCycle,setsMCmdtoDone,andsetstheordersfieldofMDatatoNoClear(othervaluesareacceptableiftheslaveisthemap).Incycle5+wthemaster(slave?)deassertsMnAdCycle.TheslaveassertsthedataonMDataandthemasterdeassertsMnRq.4.8IOWriteFlowFigure9showsthetimingforIOWriteFlow.Cycles0through1areforarbitrationasusual.Duringcycle2themasterassertsMnAdCycle,assertsIOWriteFlowonMCmd,assertstheIOregisteraddressonMAddr.Duringcycle3,themasterassertsthewritedataontoMDataanddeassertsMnAdCycle.Followingcycle3therecanbew>0waitcycles,duringwhichtheslavedoesnotassertMnAdCycleandMCmd=Doneduringthesamecycle.Duringcycle4+wtheslaveassertsMnAdCycle,setsMCmdtoDone,andsetstheordersfieldofMDatatoNoClear(othervaluesareacceptableiftheslaveisthemap).Incycle5+wthemaster(slave?)deassertsMnAdCycle,reassertsthewritedata,anddeassertsMnRq.4.9MapRefandMapRefDirtyFigure10showsthetimingforthesetwotransactions.Cycles0through1areforarbitrationasusual.Duringcycle2themasterassertsMnAdCycle,assertsMapRef(orMapRefDirty)onMCmd,assertsthevponMAddr[7..32).Duringcycle3,themasterdeassertsMnAdCycle.Followingcycle3therecanbew>0waitcycles,duringwhichtheslavedoesnotassertMnAdCycleandMCmd=Doneduringthesamecycle.Duringcycle4+wtheslaveassertsMnAdCycle,setsMCmdtoDone,andputsrp,orders,andflagsontoMData.Incycle5+wthemaster(slave?)deassertsMnAdCycle.FORINTERNALXEROXUSEONLY���qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîEqï_/î¤îf�îíîLîþî#«î&:
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éïQžî"ïS×þDæ�$î"ïP‚þDæ�$îÍïQžî”ïLž�î”ïN×�~îÍï;¬îÍï=V}îéï7~îxïJ¬îxïOø�ú�îxï0}øÿúÿî”ïÕ~îxïF:ðAø�ú�îxïAÈîxï=Vð&îxï9+ð7øÿúÿîxï4rð?rø�ú�ïî Ùî#­î*$î.Ÿî1Gÿ�������À��������TVm$������������������������������COMMONMBUSSPECIFICATIONS246+w32BA5+w1ABABABABABAB0PhaseCycleBAw cycles(w>=0)requestor: MnRq _ FALSE;arbiter: MnGnt _ FALSE;4+warbiter: MnGnt _ TRUE;Figure 9. Timing for IOWriteFlowmaster: {MCmd _ IOWriteFlow; MAddr _ IOAddress; MnAdCycle _ FALSE}master: {MnAdCycle _ TRUE; MData _ IOData}slave: MnAdCycle=FALSE => MCmd#Done;slave: {MCmd _ Done; MAddr _ mumble; MnAdCycle _ FALSE}master: {MData _ IOData; MnRq _ TRUE} slave: MnAdCycle _ TRUE;FORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE}øÿúÿîéï.îéï@e�îéïD×�î	wï,òþA�$î”ï-€�î”ï/¹�î[ï*Ýþ�$)îÍï*Ýþ�$)îéï3îéïIH�î”ï4+�î”ï1ò�î	wï1dþA�$î”ï8�î”ï6d�î	wï5ÖþA�$î”ï=�î”ï:Ö�î	wï:HþA�$î”ïA�î”ï?H�î	wï>ºþA�$î”ïEó�î”ïCº�î	wïC,þA�$î”ïJe�î”ïH,�î	wïGžþA�$î	wïLþA�$îéïMº�î
éïQžî"ïS×þDæ�$î"ïP‚þDæ�$îÍïQžî”ïLž�î”ïN×�~îÍï=VîÍï;¬îxïOîxïJ¬}îéï7~ø�ú�îxï0H}øÿúÿî Íï ¹~îxïF:ðBîxïAÈð*ø�ú�îxï=Vð$îxï8äð7îxï4rð>rïî Ùî#­î*$î.Ÿî1G�������Ð��������TVm$����������������������COMMONMBUSSPECIFICATIONS256+w32BA5+w1ABABABABABAB0PhaseCycleBA(w>=0)w cycles4+warbiter: MnGnt _ FALSE;requestor: MnRq _ FALSE;arbiter: MnGnt _ TRUE;master: {MCmd _ IOReadFlow; MAddr _ IOAddress; MnAdCycle _ FALSE}master: MnAdCycle _ TRUE;slave: MnAdCycle _ FALSE => MCmd#Done;slave: {MCmd _ Done; MAddr _ mumble; MnAdCycle _ FALSE}Figure 10. Timing for MapRef and MapRefDirtymaster: {MnRq _TRUE; MnAdCycle _ TRUE}FORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE}øÿúÿîéï.îéï@e�îéïD×�î	wï,òþA�$î”ï-€�î”ï/¹�î[ï*Ýþ�$)îÍï*Ýþ�$)îéï3îéïIH�î”ï4+�î”ï1ò�î	wï1dþA�$î”ï8�î”ï6d�î	wï5ÖþA�$î”ï=�î”ï:Ö�î	wï:HþA�$î”ïA�î”ï?H�î	wï>ºþA�$î”ïEó�î”ïCº�î	wïC,þA�$î”ïJe�î”ïH,�î	wïGžþA�$î	wïLþA�$îéïMº�î
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