///CommonMBusSpecs.tiogaWrittenby:Sindhu,September1,19841:51:14pmPDTLastEditedby:Sindhu,March22,19859:17:20pmPSTLastEditedby:Barth,December13,19842:08:47pmPSTLastEditedby:McCreight,March22,19855:13:37pmPSTCOMMONMBUSSPECIFICATIONSTheCommonMBusDescriptionandSpecificationsDRAFTofMarch22,1985..nearlydone..Releaseas[Indigo]Documentation>CommonMBus>CommonMBusSpecs.tioga,.presscCopyright1985XeroxCorporation.Allrightsreserved.Abstract:ThismemoproposesacommonMbusforDragonandCworkstation.ItisintendedtobeusedbothasaconvenientsourceforinformationabouttheMbusandasareferencemanualforbusspecifications.ThememobeginswithabriefoverviewoftheMbus.Itthenlistsallthebussignalsanddefinesthemeaningofeachsignalgroup.Next,itusesthesesignalstodescribeindetailhowthebusoperatesatboththecycleandtransactionlevels,andhowcertaintransactionsareusedtomaintaincacheconsistency.Finally,itgivesthedetailedtimingofthebustransactionscurrentlydefined.XEROXXeroxCorporationPaloAltoResearchCenter3333CoyoteHillRoadPaloAlto,California94304ForInternalXeroxUseOnlyp_,]<@!#j&+-[E"$?',n.Z6E#%T(-/XE $&&c).0qVrVVqVVrVVq(VrV sM #tH D CH P$W@Su;e;v;;g=:>w5Hu5H9 #%(x1v1R 5'(/a147=<@0R f"n$&*.12 :?. 6!$z&e'.<3c58c)RF")+*-/224S7:<?F(  q#%R'=+/5 9:x>&f(3w"&6),&2488; ?0$ Wc!& /E157=# #&,1369 !pyv.2 5.25&;.2Y7c9.25 <6t I"=& TVm$COMMONMBUSSPECIFICATIONS2Contents1.Introduction2.BusSignals3.BusOperation4.BusTimingFORINTERNALXEROXUSEONLYqgr gg!q& gg'r(gg)q+&grg+ vgEz^{[0 XX0U 0Q0r #*$.1GkTVm$_COMMONMBUSSPECIFICATIONS3 1.IntroductionTheMbusisahighbandwidthsynchronousbusthatinterconnectsamultiprocessorsystem.FivekindsofdevicesconnecttoanMbus:caches,thatintermediatebetweenprocessorsandthebus,memories,someofwhichmaybemultiported,I/Odevicecontrollers,amap,responsibleforinformingthecachesaboutthecurrentvirtual-to-physicalmemoryaddressmapping,anarbiter,thatassignsmastershiptoatmostonerequestingdevice.ThisdocumentisthespecificationfortheMbusinterfaceofcaches.ItimpliesrestrictionsonotherdevicesthatconnecttotheMbusaswell,butitisnotintendedtospecifythosedeviceswithanycompleteness.MbuseshaveabriefbutinterestinghistorywithinXerox.Thecacheconsistencyprotocol,whichmanyconsidertobethekeyideathattheMbusimplements,firstoccurredtoDashiellofXeroxEDandThackerofXeroxPARCabout1980.TheoriginalintentionwasthatEDandPARCdevelopacompatibleMbusthatcouldbeusedbyPARC'sworkstationprojectsandED'sprinterprojects.Notenoughenergywasdevotedtoovercomingtheincreaseofentropy,andbysummerof1984EDnearlyhadaworkingMbusandPARChadapaperdesignofaratherdifferentMbus.SincethenithasbecomeclearthattheEDMbusasitexiststoday(weshallcallthattheESSMbus)willnotsatisfyallofED'srequirementsforitsplannedCworkstationline,andsoconsiderableeffortisbeingdevotedatEDandPARCtosettlingonacommondesignforthesecond-generationMbus.ThisdocumentisthefirstdetailedproposalfromPARCinthatdirection.ManyoftheapparentlyarbitrarychoicesinthefollowingsectionsaredictatedbyastrongdesirethatexistingESScachesfunctionaswellaspossibleonthenewcommonMbus.Theremainderofthedocumentgoesintogreaterdetailaboutthestructure,operation,andtimingoftheMbus.Thenextsectionliststhebussignalsindetailandgivesthemeaningofeachsignal.Section3nextusesthesesignaldefinitionstoexplainhowthebusoperates:itdiscussesarbitration,liststhesetofbuscommandscurrentlydefined,showshowthesecommandsareusedineachofthepossibletransactions,showshowtransactionsareusedtomaintaincacheconsistency,andintroduceshousekeepingoperationstodealwithaddressspaceswitchesandmultiportmemories.Finally,Section4discussesthetimingofarbitrationandofeachtransactionindetail.2.BusSignalsAnMbusconsistsofthreeindependentgroupsoflines.Thefirstistheclockinggroup.Thesecond,calledthearbitrationgroup,assignsbusmastership.Thethird,calledthetransfergroup,transportsdataoncemastershiphasbeenestablished.Thefollowingdescriptionusesthesenamingconventions:S[a..b)denotesagroupof(b-a)linesthatencodethebitsrepresentingthesignalS;mostsignificantbitsofthesignalarewrittenleftmost,andhavethesmallestnumericindex.Asignalrepresentedbyasinglewireiswrittenunencumberedwiththe[)notation.Allsignalsareassumedtofollowpositivelogicunlesstheyhavean"n"asthesecondFORINTERNALXEROXUSEONLYqgr gg!q& gg'r(gg)q+&grg+ vgEz^ q[b~o!), 148 @Y r $K&*/135]X{ "u' .{123V#9#&' T5 RG+ !%,n/59=TP'"g',N! ()+I.1Q 8L6w &(+-,/5#6;=VJ T "')r+-0147Y89R?_ #|(+/43:;=4>(\= $^&+-3#57= ><^}&B U"%),-1s57^8yS+#1P"_'L,?-037Q;O )|o!B"}#)W 0R2517,8;9'"%,/248O:B<&- #U &(+-37 ?g$ n  $u&(+04)9j;"(!d")+02 9<>!7 z qK! ).7/36k9&:up<KK=Rqk]p!"g q(d,1D3 ;>]p9q3 $'+: 2 47  "8%d) .G 7@;@`9"%`( /2Y6O8; 2tnIp 122 q$22%(>+up-22.Iq228.<>3  2!v#( 1479? bf%!n&).)1I469^;=r #*$.1G bTVm$COMMONMBUSSPECIFICATIONS4characterofthesignalname.Someoftheselineshavepullupresistorstoensurethattheyremainunassertedduringcycleswhentheyarenotdriven.Theseresistorsdonotsupplyenoughcurrenttode-assertalineinonecycle;howevertheymustde-assertthelineinaminimumresetperiod.2.1ClockingGroupTheMbusistimedincyclesofatwo-phaseclock.ThephasesarenamedAandB,andaclockcyclebeginsattheleadingedgeofAandendsatthetrailingedgeofthefollowingB.AsignalthatconformstostandardMbustimingisdrivenontotheMbusassoonaspossibleafterthestartofphaseA,andissensedfromtheMbusbylatchesthatareopen(enabled)duringphaseB.ThismeansthatthelargestportionofaclockcycleisavailablefordatatopropagateandstabilizeontheMbus.AllofthefollowingsignalsexceptMPhAandMPhBconformtostandardMbustiming.MPhAThisisassertedduringthe"first"phaseofatwo-phaseclockcycle.MPhBThisisassertedduringthe"second"phaseofatwo-phaseclockcycle.MHoldThestateofthislineassampledattheendofcycleidetermineswhetherthestateoftheMbussystemattheendofcyclei+2istobeidenticaltoitsstateattheendofcyclei+1.MnResetThislineisheldassertedduringpower-up,andisassertedforatleast128consecutivecycleswheneveritisasserted.ThecyclefollowingthecycleinwhichMnResetisde-assertedisavalidMbuscycle.2.2ArbitrationGroupThearbitrationgroupconsistsofapairofrequest/grantlinesforeachbusrequestor,andoneothersharedlinecalledMnNewRQ.Asingle,centralarbitertime-multiplexesthetransfergroupamongseveralcontendingdevices.Eachofthesedevicesmakesrequeststothearbiterusingitsdedicatedrequestline,andthearbitergrantsmastershipofthebususingthededicatedgrantlines.Adevicethathasbeengrantedthebusiscalledbusmaster.Thesequenceofcyclesinitiatedbyamasterwilltypicallyinvolveatleastoneotherdeviceonthebus;suchadeviceiscalledaslave.MnRq[0..16)FORINTERNALXEROXUSEONLYqgr gg!q& gg'r(gg)q+&grg+ vgEq_/\u*!)%*,~036;Y [ !$5).358=4YeN\! #'-04%9JB: !^$*/c3F58<?H/N!#(*-/58=?G2AZ %N).&05D:<ESpB;q>)a"1&j*K,-.37Dp;q8L)a"1(#,-.5j8p4q1> &:'*M-.2Z3O :c?0$_J~!(#&a(++.06139;X=C@._A%p+q'"Z'-02i7:T<(?& JT "#),006V8$q5 R#O%)'{ /qV %.'"(+p-VV.q1VpV2ZqV6-9<? pI#^&6*O249=5y i$P(-/ 419<>`p``Rq` %E(*058;Y=pq s N#&;,c/35c9Xqsp!"+q&f)I/<15:rPJbB &k( *04*7 <?N>!N"&)h-r34:=VpKSqHZ &(z*/h178:=F\8 t#D(*,-137:p;@oD GQ! ')+/25/78<{Aeq>|"$B -C/(p:q7uq %),-1T79<5Yb &)+.2s46j;" 4&h!$(;),S1 p0q-~ ( #%[)-H1O 94 + z!$W&i(+. 48<?*8$)q,b.)2O5 ='>(oh4!# *+/%A |" =!U#+,3p53:=b?!v!&&*-.248;>v  "%g(. 0489:@";" +J.4:?' sX"[3b "T*++13 < !%(+168d 2FZ!(*5 2!4 < Aw^"%(M.2wr #*$.1GTVm$mCOMMONMBUSSPECIFICATIONS6MParityThislinecarriestheparityofMTransport.TheparityisoddanddrivenonecyclelaterbythedevicethatdroveMTransport.MnSharedThislineindicatesthatacopyoftheaddressedmemorywordispresentinaslavecache.Thislinehasapullupresistor.MnAbortThislinepreventsmemoryfromrespondingtoaReadQuadandallowsacachetorespondinstead.Thiswireisnotlogicallynecessarytothecacheconsistencyprotocol,butitallowsaperformanceoptimization.Thislinehasapullupresistor.MnHousekeepingInProgressFollowinganycycleinwhichthislineisnotasserted,everycachethatisdoinghousekeepingassertsit.Followinganycycleinwhichitisasserted,everycacheactivelyde-assertsit.Twounassertedcyclesinsuccessionmeanthatnohousekeepingisinprogress.Thislinehasapullupresistor.MnErrorThislineisusedtosignalabuserror.Theonlybuserrorcurrentlydefinedisbusparityerror.Thislinehasapullupresistor.3.BusOperationMbusoperationisspecifiedattwolevels:cyclesandtransactions.Asexplainedearlier,acycleisonecompleteperiodofthesystem-widetwo-phaseclock.Atransactionisasequenceofcontiguouscyclesinitiatedbysomebusmaster.Duringthefirstcycleofeverytransaction,MnAdCycleisasserted,MCmdspecifiesthetransactiontype,andMAddrspecifiesanaddress,whoseinterpretationvarieswithtransactiontype.Subsequentcyclestransferdata,performothermanipulations,orsignaltheendofthetransaction.Recallthatthedevicethatinitiatesatransactioniscalledthebusmaster,andotherdeviceswithwhichitinteractsarecalledslaves.Busmastershipisgrantedbythearbiter.Thusoverallbusoperationisasimplepipelinedcyclicprocessofarbitrationfollowedbytransactionexecution.Thedescriptionbelowfirsttakesuparbitration.ItthendescribesthevariousMbuscommandsaswellasthesetoftransactionsthatusethesecommands.Forcompleteness,italsodiscusseshowcachesmaintainconsistencyofmultiplecopiesofshareddata.Finallyitdiscussesasetofhousekeepingoperationsthatdealwiththemappingproblemsintroducedbymovingaprocessorfromoneaddressspacetoanother,andwiththeconsistencyproblemsintroducedbymultiportmemories.ThedetailedtimingofarbitrationandofeachofthetransactionsisnottakenupherebutislefttoSection4.3.1ArbitrationFORINTERNALXEROXUSEONLYqgr gg!q& gg'r(gg)q+&grg+ vgEp_:q[v"$K ,/35h8G;?rZDUzv $ pVqSg K!$&)7/5&8:F?0@QI 6 `$pNqKbd"E% ,.]/6]9 =1>RI' O"$&,U24k6: H) % .1468<pDqAv ,#&})/*-26C: <>=? &%Z(%+-13W4p:??;Cq?>R>'  %p)G* 1L479 <NE_ !&p91q5w"!"%),/2_5;@4;yp"#-'z- q*OgN"$t' +6/1 9;(*x#(=*8, 4;@p' q'4U4 &*0258=U%Yz7) %-/B5 : ?# h1!7&(.2V ;?"   !m%r*-3[7 @Z c@. $(\+4-149;" VV\- $)e,0179= Mn!$ )-914:7<@o7= #b)\ 0?2,8=?F/l !E$%)%*-h 46}9<? ^cD{  r #*$.1G*TVm$COMMONMBUSSPECIFICATIONS7ThesignalsinvolvedinarbitrationaretheMnRq-MnGntpairsrunningtoandfromeachpotentialmasterandthearbiter,andasinglelineMnNewRqusedtoincreasethefairnessofarbitration.Adevicerequeststhebusbyassertingitsrequestline.IfoneormoreMnRqlinesareasserted,andthereisnomaster(grantee)atthemoment,thearbiterperformsagrantcycleinwhichitissuesthebusbyassertingMnGntforadevicethathasMnRqasserted.ThebusmasterkeepsMnRqassertedwhileitstillwantsthebus,andthearbiterinturnkeepsthatmaster'sMnGntasserted.Ifthemasterisexecutingalongsequenceofcyclesthatisnotrequiredtobeatomicwithrespecttootherdevices,itmayassertMnNewRqtoindicateitswillingnesstogiveupthebusifthereareotherrequestspending(forcorrectoperation,MnNewRqmustbeassertedonlybythecurrentmaster).MnNewRqcausesthearbitertodoagrantcycleeventhoughthecurrentmasterstillhasMnRqasserted.Thisstrategypreventsamasterfromhoggingthebus(unless,foratomicity,itneedsto).Atthesametime,itavoidswastingcyclesinthecasethatnodevicesarewaitingtogetthebus.Asolutioninwhichthemasterreleasesandreacquiresthebus,forexample,doeswastecyclesinthiscase.3.2MBusTransactionsTherearecurrentlyninemastertransactions:ReadQuad,WriteQuad,WriteSingle,MapRef,MapRefDirty,IORead,IOWrite,IOReadFlow,andIOWriteFlow.Thebusmasterinitiatesamastertransactionbyassertingtheappropriatecommandwithanaddressofsomekind.ThiscommandandaddressisinterpretedbyeverydeviceattachedtotheMbus,andoneormoredevicesdecidetoactasslavesduringtheremainderofthetransaction.Somemastertransactionsconsistofafixedsequenceofcycles:WriteSingle,IORead,andIOWrite.Othersareflow-controlledbytheMnDVline:ReadQuadandWriteQuad.Theremainderareflow-controlledbytheslavetransactionDone.Flow-controlledmastertransactionsbeginwithafixedsequenceofcycles,dependingonthetransaction,waitfortheirflow-controllingevent,andthenterminateinafixedsequenceofcycles,againdependingonthetransaction.Flow-controlledtransactionsmustselectexactlyoneslave.TheMbusspecificationincludesmeansfordetectingwhenthisisnotso.(Ohyeah?Howdowedothis?WhateveriseasiestforEDshouldprobablyprevail.)Transactionsthatareflow-controlledbyDonemaycontainsubtransactionsthatarenotflow-controlledbyDone.Duringthosesubtransactions,theslaveofthemaintransactionactsasmasterofthesubtransaction.IOdevicesmayrespondtoanyorallofthefourIOtransactions.MbuscommandsarecarriedintheMCmdfieldandarevalidwhenMnAdCycleisasserted.Twelveofthesearecurrentlydefined,andtheotherfourarereservedforfutureuse.Inthedescriptionbelow,thedecimalnumberincurlybracketsafterthecommandnameindicatestheencodingofthecommand.(Onpage8ofthe21Jan84ESScachespecification,thereare(optional?)waitcyclesappearingbeforeseveraltransactions.Whatdoesthismean?)ReadQuad{0or2(sigh!)}ThiscommandisissuedbythemasterduringthefirstcycleofaReadQuadtransaction,whichreadsaquadintothemasterfrommemoryorfromanothercache.FORINTERNALXEROXUSEONLYqgr gg!q& gg'r(gg)q+&grg+ vgEq_/~ ; ')V+ 58}=?g]o @#%*-q.25= @o[XB $[%*/D145;=IZ9(] $)&,..24 6":@X+$~#D$W'+1,0258:M^!i (/h25:b=?L*{ $'T+-z/04H7;?Ja! &).475B9<H, "5&(*- 0p359G>'G4C\T w"'),=.24C9;?ER\ !$&)-p.EE/qE259;g> {B> q> k$a) 2: =H h )/s6 ?g; ?9$)+!/ 7U9?9 :!&u('+/29;@8R %f')t+O.>035f8=6r]-%'~) 4/J !&()-35:; 2Z"u$.037;80 #/%/"1$36 =/9 $(:+<,M/57";Y- "H $&.R25p8?@+`HP!(*-$ )p" $#( ,K1g49=-?' 3 {"(,d/ 0{2r6&''68p;>@J&!S"$(-q&!3 >Ab!#s)Z+-sr4/ "& ,/1 729<U "9$Tpv/cq ~d!8#V%*k.14{89;8  "$'+l.459=r #*$.1G TVm$COMMONMBUSSPECIFICATIONS8Aquadisfourcontiguous32-bitwordsalignedinphysicaladdressspacesuchthattheaddressofthefirstwordis0MOD4.DuringthisfirstcycleMAddristhephysicaladdressofoneofthewordsinthequad.ThetransactionthenconsistsofzeroormorewaitcyclesuntiltheMnDVlinesignalsthatthememorysystemisresponding.TheaddressedwordwillbeassertedonMDatabytheslaveduringthatcycle.TheremainingwordsofthequadwillbeassertedonMDatabytheslaveinsubsequentcyclesinanorderdeterminedbytheiraddressMOD4:AddrTransportorder0=>{0,1,2,3}1=>{1,0,3,2}2=>{2,3,0,1}3=>{3,2,1,0}Cachesbuilttothisspecificationwillunderstandboth0and2asencodesforReadQuad,butwillissueonly0.WriteQuad{1or3((sigh!)}ThiscommandisissuedbythemasterduringthefirstcycleofaWriteQuadtransaction,whichwritesaquadfromthemastertomemoryandtoothercaches.InthefirstcycleMAddrcarriestheaddressofthequadwhich,unliketheaddressforaReadQuadtransaction,mustbe0MOD4.InsubsequentcyclesthemasterassertsthedataofthequadonMData,inorderofincreasingaddress.ThemasterreleasesMnRqforthistransactioninthecycleafterMnDVisassertedbytheslave.Cachesbuilttothisspecificationwillunderstandboth1and3asencodesforWriteQuad,butwillissueonly1.WriteSingle{7}ThiscommandisusedbythemasterduringthefirstcycleofaWriteSingletransaction,whichwritesasinglewordintothephysicaladdressspace.WriteSingleneverwritesthewordtomemory,butonlytocachesthatalreadyholdacopyofthequadcontainingthewordbeingwritten.MAddrcarriesthephysicaladdressofthewordinthefirstcycleofthetransaction.Thedataisassertedbythemasterinthenextcycleofthetransaction.MapRef{12}Thiscommandisusedbythemasterduringthefirstcycleofavirtual-to-physicalpagetranslationtransaction.Useofthistransactionindicatesthatthemasterintendstoreaddatainthereferencedpageofitsvirtualaddressspace(eachmastermaybeoperatinginadifferentvirtualaddressspace).InthatfirstcycleMAddr[7..32)containsavirtual512-byte-pagenumber.Thefinalcycleofthetransactionisthecycleinwhichtheslave(map)assertsaDonecommandthatcontainstheresultsofthetranslationinMAddr.(DoestheESScachereallyrequirethreedeadcyclesaftertheDone?Isthatbecauseitsmatcheristiedup?)FORINTERNALXEROXUSEONLYqgr gg!q& gg'r(gg)q+&grg+ vgEq_/py_/_/*q_/L[ W#Y'p,N.3_8T<?P]nk!#Kr$]]%q](1*/2_5d9>&?[/~7!%'Q)Ye #%|(*S-048;:?gWMr"R# +.}48S:<V=!$o(+167:=@-To{"# *.0A25 <>RrRRqR$PLSMn8KTn8Hn8F]n8Cj: &1( 0+3{478:?B: M!p>q;Z!$#=%*G.1R4H79:9 Ns#c&)Y-/5+79=v8L) "%_*U,.26:=46B !$&r(66)q6+~-/ 7;+=45_ F"P'`),. 5:=3VQ% $%(+.3x4:<>_/3j: &1( 0+3{478:?- b"p*< fq&n e"%).@037a9B: %E /72U#9&)+1,6: #X$'9*k,2038n;<@e!= l!J%*/367;@e OC{) #C +-02i79;@pAQ} pX#q&A!#Y'+.504>56a  u#/$'a .J368=JK !e$&[(1,1l58=.@-=(p#(.-/259 k[ ")+,/^247+ >=?Uo!&1'[+%14T9<@eU -rN"$&*-)1 369<> u ^y3V #*$.1G*TVm$#COMMONMBUSSPECIFICATIONS9MapRefDirty{10}Thiscommandisusedbythemasterduringthefirstcycleofavirtual-to-physicalpagetranslationtransaction.Useofthistransactionindicatesthatthemasterintendstowritedatainthereferencedpageofitsvirtualaddressspace(eachmastermaybeoperatinginadifferentvirtualaddressspace).InthatfirstcycleMAddr[7..32)containsavirtual512-byte-pagenumber.Thefinalcycleofthetransactionisthecycleinwhichtheslave(map)assertsaDonecommandthatcontainstheresultsofthetranslationinMAddr.IORead{4}ThiscommandisusedbyamasterduringthefirstcycleofanIOReadtransaction.MAddrcontainstheIOregisteraddress.Thesecondandthirdcyclesareidle.AnynumberofdevicesmaygeneratesideeffectsinresponsetoanIORead,butexactlyoneslavemustassertdataonMDataduringthefourthcycle.TheinterpretationofanIOReadisentirelyuptotherespondingdevice.Thusitmayactuallyreadfromarealdeviceormaycausesomesideeffect,orboth.IOWrite{5}ThiscommandisusedbyamasterduringthefirstcycleofanIOWritetransaction.MAddrcontainstheIOregisteraddress.ThemasterassertsthedataonMDatainthenextcycle.Anynumberofslavesmayrespond,buttheydosoundetectedbytheIOWriteprotocol.IOReadFlow{8}ThiscommandisusedbyamasterduringthefirstcycleofanIOReadFlowtransaction.MAddrcontainstheIOregisteraddress.TheslavesignifiesreadinessbyaDonecommand,andassertsdataonMDatainthefollowingcycle.IOWriteFlow{9}ThiscommandisusedbyamasterduringthefirstcycleofanIOWriteFlowtransaction.MAddrcontainstheIOaddress.DuringthesecondcyclethemasterassertsdataonMData.InsomesubsequentcycletheslavesignifiesreadinessbyaDonecommand,andthemasterre-assertsthesamedataonMDatainthefollowingcycle.Done{14}Thiscommandisissuedbytheslavedevicetoflow-controlaMapRef,MapRefDirty,IOReadFlow,orIOWriteFlowtransaction.ThevaluethatitassertsonMAddrdependsonthetransactionandtheslave.IfthetransactionisMapReforMapRefDirty,thentheslaveisthemap.MAddr[0..25)containsthenumberofthe512-bytephysicalpagecorrespondingtothevirtualpagethatinitiatedthetransaction.MAddr[25..28)carriesoneofthefollowingorders:NoClear{7}--noactionrequiredFORINTERNALXEROXUSEONLYqgr gg!q& gg'r(gg)q+&grg+ vgEp_, 3q[&A!#Y'+.504>56Z6  u#/$'a .J368=JX !$&(Y,1518=5@-V=(p#(.-/259 U@[ ")+,/^247+ >=?SUo!&1'[+%14T9<@eQA pNqKS!>#% ).1z48:<I !3#%*0|3\7:>'Hybt"%+-239%:<F]c{#E&J(Q-1t38Cy  %'W,S.c02k 9>B;8<Sm"&(+/v3 5:;p>hq;!*#%).1M4~8J:\<9 !\#%*038E<?8N!$)+/28;>?@Z6 Fp3X q0 d Q"o#(O,/d2_579 .b !7#%*03f6<,,C#&(-P.1^7pp)k ?q&Z ="V#(+,/72-579 $u !Q#%+037;>="4<E#B *o-0G39>@!'SW" (*.p1k3h89< p0q3 "$'+0^2 :p t$&(.4 7d @oA!#t N ?!#&, 6BI!ar #*$.1GTVm$COMMONMBUSSPECIFICATIONS10ClearRPDirty{6}--writepermissionforthecurrentphysicalpageissummarilycancelledinallcaches.Fromthispointon,anycachewishingtowritetoavirtualaddresslyinginthisphysicalpagemustacquirenewpermissionviaMapRefDirty.ClearVPValid{4}--virtualmappingstothecurrentphysicalpagearesummarilycancelledinallcaches.Fromthispointon,anycachewishingtoreferencethisphysicalpagemustacquireanewvirtual-physicallinkageviaMapReforMapRefDirty.WriteProtectFault{2}--aMapRefDirtyfailedtoacquirewritepermissionfromtheslave.ThisorderisofinterestonlytotheMbusmaster.PageFault{1}--theslavefailedtolocateavalidvirtual-to-physicalmapping.ThisorderisofinterestonlytotheMbusmaster.MAddr[28..32)carriesagroupoffourflagsfromwhichthemastercacheshouldupdateitsmappinginformation(exceptifthereisaPageFault):MAddr[28]--reservedMAddr[29]--writeprotect(=NOTdirty)MAddr[30]--dirtyMAddr[31]--referenced(=true)(Note:Theseflagsareallredundant.Theycanbeinferredfromthetransactionanditsfaults.TheyareincludedforbackwardscompatabilitywiththeESScache.)IfthetransactionisIOReadFloworIOWriteFlow,andtheslaveisnaive(ignorantofmapping),duringtheDonecyclethefieldMAddr[25..28)carriestheorderNoClear.IOdataisthentransportedinthefollowingMbuscycle.IfthetransactionisIOReadFloworIOWriteFlow,andtheslaveissophisticated(awareofmapping,probablythemapitself),thenMAddr[0..25)cancontainthenumberofa512-bytephysicalpage,andMAddr[25..28)cancontaintheordersNoClear,ClearRPDirty,orClearVPValid.IOdataisthentransportedinthefollowingMbuscycle(eventhoughthatdatamaybemeaningless;theIOReadFloworIOWriteFlowmayhavebeenexecutedforthesideeffectsofitsDonecommand).Infact,themapwillprobablycontaina"Donereflector"IOregister,thatwillsimplysavethedatasentbythemasterinanIOWriteFlowtransactionandretransmititintheappropriatefieldsoftheDonecommandthatterminatesthetransaction.Reserved{6,11,13,15}Thesecommandsarereservedforfutureuse.Cachesbuilttothisspecificationwillignorethem.3.3TheCacheConsistencyProtocolThecacheconsistencyproblemistopreventmultiplecopiesofadatumindistinctcachesfromhavingdifferentvalues.ThisproblemarisesbecauseDragoncachescontainshareddatathatmaybewritteninto.ThesolutioninvolvestheuseoftheMnSharedandMnAbortbuslinesandtwoadditionalbitssharedandownerstoredwitheachquadinacache.ForagivenFORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgEq_' D(! (m*,16:;Z]!$3'*6,057f:<=[> $!',i/W 6G8 Y] 7"=(]),*069';ZW v"t%>)+.W2L79V?|V"R$!'17d:F@ZTg QI ! *E./4p7 >PDASx$W'q)+~-Y/M-`"L&5',-=0< L" "}$&)MI  4$%%(+/>3;59=GuO "'_(,I-. E6C 6"]#Z%?(@6>6 !#r;$ M %z(d*,&0q3@5< :=+>9C & (*,q7u~6 N ') 3*698<>u5}"$({,.1 ;C?4&!&" *+.4!581e P %' 0N25E89 0i!$;'+/6 7:?.\LC#&) 3a6*;G=,'  *-j026 =?+8 M$'*-/~ 79 )f 2"(/*],/x35d70:&w$)j*/ 5E7f<?s%D1T8"&e') 2 8; #8F Z!#r'=-0l 79z p N@q$O&*-257:: W{& q> %'s)W.4;8:;@p7 I&+@.r47=2w|"J%N'?+ tn!=#%O'.X179<?r  pF q p ?q #'+7.2345V:I=>jr #*$.1GTVm$COMMONMBUSSPECIFICATIONS11quad,ifsharedisfalsethennoothercachecontainsacopyofthequad.However,ifsharedistrueothercachesmayormaynotcontainthequad(thereisuncertaintybecausewhensharingstopsthisfactisnotdiscoveredimmediately).Owneristrueifandonlyifthelastwriteintothequadwasintothisverycache.AcacheinitiatesaReadQuadwhenitgetsamiss;itissuesaWriteQuadwhenaquadneedstoberemovedfromthecachetomakeroomforanotherquad(onlyquadswithownersetneedtobewrittenbacktomemory);anditissuesaWriteSingleandsetsownerwhenitsprocessordoesawritetoaquadthathassharedset.WhenacacheissuesaReadQuad,WriteQuad,orWriteSingleallothercachesonthebusmatchthequadaddresstodetermineiftheyholdacopyofthequad.AnycachethatmatchesassertsMnSharedtosignalthatthequadisshared.DuringReadQuadsthemasterandallmatchingslavescopythevalueofMnSharedintothesharedbitforthatquad.Also,whenacacheissuesaWriteSinglethemastercopiesthevalueofMnSharedintothesharedbit.Thisensuresthatsharingisdetectedassoonasitstartsandiseventuallydetectedwhenitstops.DuringReadQuad,WriteQuad,orWriteSingle,allmatchingquadsexcepttheonesupplyingdatatothebusloadnewvaluesfromthebusandcleartheirownerbits.Theownerbitisseteachtimeaprocessorwritesoneofthewordsofthequad.Ifthequadisshared,theresultingWriteSinglewillupdateallothercopiesofthequadandcausetheirownerbitstobecleared.Thusatanytimeatmostoneofthecacheswillhaveownerset.Ownermaynotbesetatall,ofcourse,ifthequadhasnotbeenwrittenintosinceitwasreadfrommemory.DuringaReadQuad,iftheownerbitissetonamatchingquad,thatcacheassertsMnAbortandsuppliesthedatatotheMbusitself(sincethememorydoesn'tknowthecurrentvalue).OtherwiseMnAbortisnotsetandthememorysuppliesthedata.3.4HousekeepingoperationsWeareleftwithtwoproblemsthatDragonsandprobablyCmachineswillhavetodealwith,andthatthatthebasicMbusoperationsabovehavedealtwithincompletely.Thefirstiscontextswitchesbetweenaddressspaces.Whenaprocessormovesfromoneaddressspacetoanother,alloftheoldvirtual-to-physicalassociationsinitscachesthatarenotalsopresentinthenewaddressspacemustbebroken.TherearetwowaystosolvethisproblemwiththebasicMbusoperations.First,theprocessorcanissueasequenceofPbusreferencesthatvictimizesalldatainallitscaches.Second,asequenceofMbusDonecommandscanbegenerated,incooperationwithasophisticatedslave,toclearVPValidinallcachesforallphysicalpagesthatmightbeknowntotheprocessor.Bothofthesesolutionsaresoexpensiveastoprohibitfrequentcontextswitchesbetweenaddressspaces.Thesecondremainingproblemismultiportmemories.Somememorieshavetwoports,aprimaryonewhichattachestotheMbusandasecondaryonewhichdoesnot.SuchamemorymightappearinadisplaycontrollerthatcandoautonomousBitBlt,forinstance.Whenbothportsareactive,ourprotocolformaintainingconsistencydoesnotwork,becausethesecondaryportcandoreadsandwriteswithoutinformingtheMbus.Apartialsolutiontothesecondproblemistotime-multiplextwo-portmemoriesamongseveralaccess-limitedstates.AtanymomentsuchamemoryisinoneofFORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgEq_/z 7";%)/0-3}547;]<t #%w(t*/259: [ "%a&)E 0 9F=?:Z9CuT"% (+4. 03W2$P$8')G,-C02067?>iV6. $S&*,C/35;>To  "l'*(+1459: R!B#&(+r-.114e6;&>Q  A ') 1"36;=!?Oy~&G'*. /B24e6;B>RM !#T')),,/06:L*Gyn q$a'*-/6T91;@J J $~(_) 13u7<>tHT' #&+.3\4:7;?@G4v- 1"&a'D %d'; /1147E;[?C!$',/x147D:=Ak>s%!N$k%+/2436<:@;>H=Hw|?$ ,/T359=?;X "$X&A+/@03h68;j>?90G ;$'*2, .:/238r9<-?8RWg?!#&*55G #T')+}-/1<7`;]>R40 .!#_&S'*?, .158=`2$!%+-b/247Q<0A{-  q*CZ[$P' ,z/46J<@>(!#'v),{ 3s7;Q?& MH"(7-2F7;< %M;! "')+%-\/: #*1"#'(+t.37q:=!ZF #),I.2?4+6 > WAS9a$I&'V) 0l39 9;}>@.g#%%' )-479 @p [o "&i(+[024h8:<aF#d #= )-9.2F7:*;>!'U,1>>%u&-148u>"( ),L.5034;U>nwG!%*,.\3j :=0@H $) ,0G27c:0? f  #&+.)47k9;?g[ " Oy V$*<+-% 6R; 1 !%'*0,3z4:J;=@er #*$.1G RTVm$gCOMMONMBUSSPECIFICATIONS12threestates:eitheritssecondaryportisentirelyinactive,orelsetheMbushasnoknowledgeofit,orelsebothMbusandsecondaryportarepreventedfromwriting.Thissolutionisabittoocoarse.Wecanrefineitbyallowingeachpageinsuchamemorytobeinoneofthethreestatesindependentofthestatesofotherpages.TodealwiththefirstproblemweintroduceanoperationcalledDeMapping(breakingvirtual-to-realassociation,leavingorphansinthecache).TodealwiththesecondweintroduceLaundering(rewritingalldirtyquadstomemoryandleavingthemclean)andFlushing(clearingRPValid).(FlushingappearsnottobenecessaryifReadQuadsalwaysrefillcleanorphansfrommemory.LaunderingandDeMappingsufficeinthatcase.)Collectivelywerefertotheseashousekeepingoperations.Forefficiencyhousekeepingoperationsapplynottosinglephysicalpagesbutrathertosetsofphysicalpagesmatchingamaskof{0,1,don'tcare}"trits".Housekeepingoperationscanbeappliedtoallcachesatthesametime,ortoasinglecache.Eachcachecontainsapairof32-bitregistersthattogetherholdthephysicalpagemasktobeused.Inaddition,eachcachehasasinglehousekeepinginitiationregisterlocatedattwoI/Oaddresses:abroadcastaddress,andaprivateone.1bitsstoredintoappropriatebitsoftheinitiationregistercauseinitiationofDeMap,Launder,andFlush.(IfwecoulduseaddressesinESScachemailboxspace,therewouldbeawayofnotifyingprocessorsattachedtoESScachesthatthesehousekeepingoperationswerebeinginitiated.)ThisallimpliesthatacacheneedstorespondasaslavetoitsownIOWrites,andprobablytoitsownIOReadsaswell.Itisnotnecessaryforcachestorespondtoflow-controlledIO.LaundercanrequireenoughMbuscyclestotransportalldirtyquadsineverycachebacktomemory.WhileaLaundryoperationisunderwayeachcachere-arbitratesfortheMbusforeverydirtyquadthatitownsandneedstostore.RequestsfromthePbussidedemandingMbusservicehavehigherprioritythantheoperationrequests.Thesestipulationstogetherpreventahiccupfromoccuringinthesystemwhenthereisagreatdealofdirtydatatobelaundered.NotonlyLaundry,butallhousekeepingoperations,dependingontheirimplementations,maytakemanycyclestocomplete.Conceptuallyeachcachemaintainsahousekeepinginprogressbitthatindicatesthatahousekeepingoperationhasbeenstartedinthatcachebutnotyetfinished.WhetheranoperationisinprogressinanycacheinthesystemcanbeknownbyobservingthestateoftheMnHousekeepingInProgresswirefortwosuccessivecycles.Ifitisnotassertedinsomecyclei,thenanycachewithanoperationstillinprogresswillassertMnHousekeepingInProgressincyclei+1.Ifitisassertedincyclei,theneverycachewillde-assertitincyclei+1.MnHousekeepingInProgresswillthustoggleonandoffuntileverycachehasfinishedthelasthousekeepingoperation.EachcachehasameansbywhichMHousekeepingInProgress[i+1]ORMHousekeepingInProgress[i]maybereadfromitsPBuswithoutneedingMbuscycles.Thealertreaderhasalreadynoticedthatconcurrenthousekeepingoperationscouldbeanightmare.Weavoidconcurrencybymaintaining,asasoftwareconvention,aglobalhousekeepinglockinshared(andalwaysmapped)memory.Todohousekeepingaprocessmustacquirethelock,verifythatprevioushousekeepingisfinished,initiatetheoperation,and(iflogicallynecessary)holdthelockuntilhousekeepingisonceagainfinished.FORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgEq_/w# &',2369 :=@]my "|% '.1 3S9=[H x#&(,.058< =@Z9OH a#' /1G37\9<WD%e'-0 6X:rV $){.0Q279<?Tn #w )+/D3X5:=aR &r,RR-1698n:;@QP"$) /17;r<?qOx  $<& / 8; M  "%;'+;047n;=@eL)!#%&*l-2 ;p Jm^H 7!$/'+*,./3H;+ "$(.}1p6:M<F_*n`{K%(F,./3 O?|CE]  "%v +04 :<AinrAiAixW"X$H)*m,/374:=Q>??( 1n!%'2q)??* r?2U 7:= q=E#')J.0[15 68;;l#%e)0*,.46;-<9!7z4#w%R'+-3q5c8<>j5 $;%+2D4:>R4+  O"&)-02 58<>j2N,!(*-2159>0Ft! ).n3s49</5k  !>$')c,/1h3Y ,!$l - 5+8 ~$(*2, :>R)kp))k)k dq%))k)k%'5)/2N3g ;'x"m%'*&06p8>@p&vK!`&(*/x18:=?$u L#q%( / 4 578;"@p"%<#~')t03*5N;2>S!& a";%*+-7.426 9;>jJB!U%6e9 <@!&S(+5 3 :>R0o")r?00@q $&$)q- /28={?e@#(+ 2 ;p e !"&1 .W0 9;< 7M[ #&(e,/4#9?o zk"')-J1/39 M $b'L)X. 59;>  3r #*$.1G TVm$JCOMMONMBUSSPECIFICATIONS134.BusTimingThissectiongivesthedetailedtimingofbusarbitrationandofeachofthetransactionsjustdescribed.Inthetimingdiagrams,eachrowcorrespondstoonebuscyclefornon-idlecycles.Idlecyclesarerepresentedbyarowlabelled"wcycles",wherewindicatesthenumberofidlecycles.ActionsduringeachcycleareindicatedusingMesalikestatements.NotethatthebooleanvalueTRUEcorrespondstothehighvoltagelevelandthebooleanvalueFALSEcorrespondstothelowvoltagelevel.Forexampleanegativelogicsignalxwouldbeassertedasfollows:x_FALSE.ThediagramsdonotdescribethetimingofMParity,sincethisisalwaysonecycledelayedfromthevalueonMTransport.Ineachdescription,therequestorassertsMnRqincycle0andthearbiterassertsMnGntincycle1.Anarbitrarynumberofcyclesmayoccurbetweencycleslabelled0and1.4.1ArbitrationThetimingforarbitrationappearsinFigure2.ArequestorassertsMnRqduringphaseAofcycle0.ThearbiterlatchestherequestduringtheBofcycle0,andifthebusisfreeMnGntgetsassertedintheAofcycle1.Thenewmastercandrivethebusatthebeginningofcycle2A.Thustheminimumarbitrationdelayistwocycles.Ifthebusisnotfree,zeroormorewaitcyclesareinsertedimmediatelyaftercycle0.TheearliestMnRqcanbedeassertedisduringcycle2+w.TheearliestMnGntisdeassertedinresponseisduringcycle3+w,andtheearliestanewdevicecanbecomemasterisduringcycle4+w.TheearliestMnNewRqmaybeassertediscycle3+w.Itmustbedeassertedinthefollowingcycle.4.2ReadQuadFigure3showsthetimingforReadQuad.Cycles0through1aretakenupbyarbitration(recallthatweareassumingtheminimumarbitrationdelay).Thetransactionbeginsincycle2.ThemastersetsMCmdtoReadQuad,MAddrtoRQAddress,andassertsMnAdCycle.Cycles3and4donottransmitanydata.Duringcycle3themasterdeassertsMnAdCycleandduringcycle4anymatchingcacheassertsMnShared,andifitsownerbitisset,assertsMnAbort.InthefollowingcyclememorydeassertsMnSharedandthecache,ifany,thatassertedMnAbortdeassertsit.Aftercycle4theslavemayinsertanarbitrarynumberofwaitcycles,w>0.Incycle5+wtheslave(respondingcacheormemory)assertsMnDVtosignalthatdataisvalidandsendsthefirstwordofthequadonMData.Duringcycle6+wtheslavedeassertsMnDVanddrivestheseconddatawordontoMData.Duringcycle7+wtheslavedrivesthethirddatawordontoMDataandthemasterdeassertsMnRq.During8+wtheslavedrivesthefourthdatawordontoMDataandthearbiterdeassertsMnGnt.NotethattheminimumnumberofcyclesforReadQuadis7,assumingzeromemorywait.FORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgEz^ q[d%a)+. 58:o=?Y @ "p$)f/35 =?rXW;@"b&*-, 4:6]7:?Vm!t&(O+/490<\?U Ot %)7+.53Sr6U U 7qU :} Sa| T"'r+VSaSa,qSa/d 68:=aQb=>"&[p*vQqQ+0N2n79p?QqQ@rPqPP 1!'E).;059p<0=Nk~#% KYp  &*6.0!3z4729x=JIg"{')7-0 39<H{C qA/H "().129%=?U9 "'[+.F379;`=@=?0 #(*,.]03x5w8F;+?<9u!"#'@)-g/60 <@:L  #&(Z+.25:F 86oj i! (S). 1l58~=4q 8  a$(,/t168;+?3 4"W').6'9J;[@1yU; $8%(E.X{,q* "]$,@0168:b>@"(_ !')z/ 6%` ?r!$[&3(-D/4u6=)$< p6 (O,-0246<>"K %f->0 489h<   a!#d'v)w*- 1S89< F&% '*.0l36;\!%:(I, .39:=p|q#|v R '+-3l7<>3 #;&2)+.1139>-Q#&+--259= j$t&*6-9038;Q=$"%(,/&3s6:'=k7i%;*! &m(F,^.57O8? O mr #*$.1G TVm$vCOMMONMBUSSPECIFICATIONS144.3WriteQuadFigure4showsthetimingforWriteQuad.Cycles0through1aredevotedtoarbitrationasusual.Duringcycle2themastersetsMCmdtoWriteQuad,MAddrtotheaddressandassertsMnAdCycle.Duringcycle3themasterdrivesthefirstdatawordontoMDataanddeassertsMnAdCycle.Duringcycle4themasterdrivestheseconddatawordontoMDataandiftherearezerowaitstates(w=0)thememoryassertsMnDV.Duringcycle5themastersendsthethirddatawordonMDataandiftherearezerowaitstates,deassertsMnRq.ThememorydeassertsMnDViftherearezerowaitstates,orassertsMnDVifthereisonewaitstate.Incycle6themasterdrivesthefourthwordontoMData,anddeassertsMnRqifthereisonewaitstate.IftherearezerowaitstatesthearbiterdeassertsMnGnt.ThememorydeassertsMnDVifthereisonewaitstate,orassertsMnDViftherearetwowaitstates.Incycle7,iftherearetwowaitstates,themasterdeassertsMnRqandthememorydeassertsMnDV.IfthereisonewaitstatethearbiterdeassertsMnGnt.IftherearethreewaitstatesthememoryassertsMnDV.Finally,thereareanarbitrarynumberofwaitcycleswhichareterminatedbythememoryassertingMnDV,followedinthenextcyclebythemasterdeassertingMnRq,andinthenextcyclethearbiterdeassertingMnGnt.NotethattheminumumnumberofcyclesforWriteQuadis5.4.4WriteSingleFigure5showsthetimingforWriteSingle.Cycles0through1aredevotedtoarbitration.Duringcycle2themasterdeassertsMnRq,setsMCmdtoWriteSingle,setsMnAdrtotheaddress,andassertsMnAdCycle.Duringcycle3themastersetsMDatatothedataanddeassertsMnAdCycle.ThearbiterdeassertsMnGnt.Duringcycle4anymatchingslaveassertsMnShared.Duringcycle5anymatchingslavesdeassertMnShared.4.5IOReadFigure6showsthetimingforIORead.Arbitrationtakesplaceduringcycles0through1.Duringcycle2themasterassertsMnAdCycle,assertsIOReadonMCmd,assertstheIOregisteraddressonMAddr,anddeassertsMnRq.Duringcycle3,themasterdeassertsMnAdCycle,andthesingleslaveassertsdataonMData.4.6IOWriteFigure7showsthetimingforIOWrite.Cycles0through1areforarbitrationasusual.Duringcycle2themasterassertsMnAdCycle,assertsIOWriteonMCmd,assertstheIOregisteraddressonMAddr,anddeassertsMnRq.Duringcycle3,themasterassertsthewritedataontoMDataanddeassertsMnAdCycle.4.7IOReadFlowFORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgE{_,q\^v"E$ ,1 2L78;-@o[  UX("%`*M, 38:=4V #m&(!*.35v8T;_>U@- $W),t-/4J8G:?SPe!N#&p)N,p-bSqS.I1=38= Q,"$(D+=.05X89W<?PJ!g$W)/459< ?%NQ"$Y'*.10 347.;?L27"',\-1r258<>KTCT[" '-06);@It3#X()-/x2-5/9;?'@H'4v" &,1B4-6DG"=(-603L5Z;@eCu #v%'-p3%8K>?Ah@L ',//51237>:=? =EH!&-'+.5C6{8N q5Pa""$c ,1/2h78;4@o4, |B"@&,f1,38:; 2qx"k& /M478;?}0|XD" *-27=U/6bP[$*+0495z8(>3-{(q&EP"$B*Q 1v48<@$u!Q!\% -168= S5D$,&,16u9;[= o!%) -o0t2{{q:O_"$_*/0O569;Y K!>%l -e168=p5D$,&,16u9;[=1C#&,i {  r #*$.1G4TVm$COMMONMBUSSPECIFICATIONS15Figure8showsthetimingforIOReadFlow.Cycles0through1areforarbitrationasusual.Duringcycle2themasterassertsMnAdCycle,assertsIOReadFlowonMCmd,assertstheIOregisteraddressonMAddr.Duringcycle3themasterdeassertsMnAdCycle.Followingcycle3therecanbew>0waitcycles,duringwhichtheslavedoesnotassertMnAdCycleandMCmd=Doneduringthesamecycle.Duringcycle4+wtheslaveassertsMnAdCycle,setsMCmdtoDone,andsetstheordersfieldofMDatatoNoClear(othervaluesareacceptableiftheslaveisthemap).Incycle5+wthemaster(slave?)deassertsMnAdCycle.TheslaveassertsthedataonMDataandthemasterdeassertsMnRq.4.8IOWriteFlowFigure9showsthetimingforIOWriteFlow.Cycles0through1areforarbitrationasusual.Duringcycle2themasterassertsMnAdCycle,assertsIOWriteFlowonMCmd,assertstheIOregisteraddressonMAddr.Duringcycle3,themasterassertsthewritedataontoMDataanddeassertsMnAdCycle.Followingcycle3therecanbew>0waitcycles,duringwhichtheslavedoesnotassertMnAdCycleandMCmd=Doneduringthesamecycle.Duringcycle4+wtheslaveassertsMnAdCycle,setsMCmdtoDone,andsetstheordersfieldofMDatatoNoClear(othervaluesareacceptableiftheslaveisthemap).Incycle5+wthemaster(slave?)deassertsMnAdCycle,reassertsthewritedata,anddeassertsMnRq.4.9MapRefandMapRefDirtyFigure10showsthetimingforthesetwotransactions.Cycles0through1areforarbitrationasusual.Duringcycle2themasterassertsMnAdCycle,assertsMapRef(orMapRefDirty)onMCmd,assertsthevponMAddr[7..32).Duringcycle3,themasterdeassertsMnAdCycle.Followingcycle3therecanbew>0waitcycles,duringwhichtheslavedoesnotassertMnAdCycleandMCmd=Doneduringthesamecycle.Duringcycle4+wtheslaveassertsMnAdCycle,setsMCmdtoDone,andputsrp,orders,andflagsontoMData.Incycle5+wthemaster(slave?)deassertsMnAdCycle.FORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgEq_/fL#&: /46);=;?] U[p!&G .d2 :<Y_iTk"$+ 0 35#7|>q>:j k% '+/27?g=, $)/379=;  j$'p*',0405:<9, "%(*M,137W;=86 !')x,0S3 8{34v q0x"%(+W 389T>?/  ,M!H%x -s169 *I9T!{ +(035R7$#;d;d$0H$ $#25$/O$/O$/+$x) ,$&k$&k$&G$$$$$c$x xC,$ ]$x+$%?>$%?83$+83$%?8$&;&:H%?3$%?-$+-$%?,$&0&/+)9$A?$.[E ?G!V$?!z$2$.2j$r2 $r+;dy$/@0k$ +0Hy$/@5 9$2$2 $0\] $;y<$Ey=Ey;dB$5 @$MA5$ VB$5$ VB$C, $;y($Ey)Ey'dB$! @$MA!$ VB$!$ VB$/+ $D D=$ ?c$?1$ VOz1$ V?$;yr$$#*r #*$.1GOTVm$=COMMONMBUSSPECIFICATIONS17Figure 2. Timing for Bus Arbitrationarbiter: latch request;4+w3+w2+w(w>=0)w cyclesABABABABAB0PhaseCycleBA<><>1+wrequestor: MnRq _ FALSEarbiter: MnGnt _ FALSE;<><>; MnNewRq _ TRUE;FORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgE})$~L3$ :?3$ :} [7 [; [@e~ ?Hs J}86d 5:$=: :H:$A?H >:$EC C,:$JeH, G:$ L:$ [M[Q S>;$ P>;$ ?QLN~A8} D~OF:(A5=V3r #*$.1GfTVm$COMMONMBUSSPECIFICATIONS18Figure 3. Timing for ReadQuad8+w7+w6+w32w cycles(w>=0)BABABA5+w1ABABABABABAB0PhaseCycleBArequestor: MnRq _ FALSE;arbiter: MnGnt _ FALSE;4slave: {MData _ RQData0; MnDV _ FALSE};AB9+wslave: MParity _ RQData3Parityslave: {MData _ RQData1; MParity _ RQData0Parity; MnDV _ TRUE}slave: {MData _ RQData2; MParity _ RQData1Parity} master: MnRq _ TRUE;w=0 => {some cache: owner => MnAbort _ TRUE; memory: MnShared _ TRUE}master: {MCmd _ ReadQuad; MAddr _ RQAddress; MnAdCycle _ FALSE}master: MnAdCycle _ TRUE;any cache: {match => MnShared _ FALSE; owner => MnAbort _ FALSE}; waitCycle _ 0;memory: MnShared _ TRUE}(waitCycle _ waitCycle+1)=1 => {some cache: owner => MnAbort _ TRUE; slave: {MData _ RQData3; MParity _ RQData2Parity} arbiter: MnGnt _ TRUE;FORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgE}!\ "! "&G "* "@e "D~ 7 6 )?W$})+ $?W$%+'d +?W$ "$:$: "0H "IH2. -?W$84 4+?W$=: :H?W$A?H >?W$EC C,?W$JeH, G?W$ L?W$ "M"Q[SB$[PB$ QLN~OJ} ";~2'}G ?W$ "c~,>'G1EF:?A=VP7:8E#9Hr #*$.1GTVm$XCOMMONMBUSSPECIFICATIONS19Figure 4. Timing for WriteQuadABCyclePhase0BABABABABABA1ABAB23requestor: MnRq _ FALSE;arbiter: MnGnt _ FALSE;master: {MCmd _ WriteQuad; MAddr _ WQAddress; MnAdCycle _ FALSE}4567master: {MData _ WQData0; MnAdCycle _ TRUE}w=0 => memory: MnDV _ TRUE; w=1 => memory: MnDV _ FALSE;master: {MData _ WQData2; MParity _ WQData1Parity; w=0 => MnRq _ TRUE}master: {MData _ WQData3; MParity _ WQData2Parity; w=1 => MnRQ _ TRUE}w=0 => memory: MnDV _ FALSE;master: {MData _ WQData1; MParity _ WQData0Parity} (w>0)w=0 => arbiter: MnGnt _ TRUE; w=1 => memory: MnDV _ TRUE; w=2 => memory: MnDV _ FALSE;w=1 => arbiter: MnGnt _ TRUE; w=2 => memory: MnDV _ TRUE; w=3 => memory: MnDV _ FALSE;waitCycle=w-2 => arbiter: MnGnt _ TRUE; waitCycle=w-4 => memory: MnDV _ FALSE;waitCycle _ waitCycle + 1; waitCycle=w-3 => {master: MnRq _ TRUE; memory: MnDV _ TRUE}w-1 cyclesmaster: {MParity _ WQData3Parity; w=2 => MnRq _ TRUE}; waitCycle _ 1;FORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgE}!\NLQ"PD$"SD$ Q wM wLA$ wGA$H,Je wC,A$CE w>A$?HA w8A$8= w1dA$16d w*A$+G/ wIH $6t[$6t"d wcA$)$ w$A$ wD w@e~xOxJxF:@} w: w4+ w. w&~xB+58x6Fx0F;x=V3U.VV'V!Nx"V! x)VEr #*$.1GTVm$7COMMONMBUSSPECIFICATIONS20ABCyclePhase0BABABABA123Figure 5. Timing for WriteSingle4requestor: MnRq _ FALSE;arbiter: MnGnt _ FALSE;master: {MnRq _ TRUE; MCmd _ WriteSingle; MAddr _ WSAddress; MnAdCycle _ FALSE}master: {MData _ WSData; MnAdCycle _ TRUE}; arbiter: MnGnt _ TRUE;master: MParity _ WSDataParity; slave: match => MnShared _ FALSE;AB5slave: match => MnShared _ TRUE;FORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgE}NLQ"PG$"SG$ QM wLC$ wGC$H,Je wC,C$CE w>C$?HA w:HC$:=IH 3$ :[3$ :D@e$<~xOxJxF:OxBBx=A}86d w5C$8~x8r #*$.1GTVm$COMMONMBUSSPECIFICATIONS21321ABABAB0PhaseCycleBAFigure 6. Timing for IOReadrequestor: MnRq _ FALSE;arbiter: MnGnt _ FALSE;master: {MCmd _ IORead; MAddr _ IOAddress; MnAdCycle _ FALSE; MnRq _ TRUE}master: MnAdCycle _ TRUE; slave: MData _ IOData; arbiter: MnGnt _ TRUE;FORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgE}@eD[<$V <$VIHA?H w>A$EC wC,A$JeH, wGA$ wLA$M Q"SD$"PD$QLN#&G~xOxJxF:JxAGr #*$.1G"TVm$COMMONMBUSSPECIFICATIONS22321ABABAB0PhaseCycleBArequestor: MnRq _ FALSE;arbiter: MnGnt _ FALSE;Figure 7. Timing for IOWritemaster: {MCmd _ IOWriteFlow; MAddr _ IOAddress; MnAdCycle _ FALSE; MnRq _ TRUE}master: {MnAdCycle _ TRUE; MData _ IOData}; arbiter: MnGnt _ TRUE;FORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgE}@eD[<$V <$VIHA?H w>A$EC wC,A$JeH, wGA$ wLA$M Q"SD$"PD$QLN~xOxJ} +~xF:OxABr #*$.1G#TVm$COMMONMBUSSPECIFICATIONS236+w32BA5+w1ABABABABABAB0PhaseCycleBA(w>=0)w cycles4+warbiter: MnGnt _ FALSE;requestor: MnRq _ FALSE;arbiter: MnGnt _ TRUE;Figure 8. Timing for IOReadFlowmaster: {MCmd _ IOReadFlow; MAddr _ IOAddress; MnAdCycle _ FALSE}master: MnAdCycle _ TRUE;slave: MnAdCycle _ FALSE => MCmd#Done;slave: {MCmd _ Done; MAddr _ mumble; MnAdCycle _ FALSE}slave: {MnADCycle _ TRUE; MData _ IOData}; master: MnRq _ TRUE;FORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgE}.@eD w,A$-/[*$) *$)3IH4+1 w1dA$86d w5A$=: w:HA$A?H w>A$EC wC,A$JeH, wGA$ wLA$M Q"SD$"PD$QLN~;=V}7~xJxOx0}~xF:AxAx=V&x9+7x4r?r #*$.1GTVm$COMMONMBUSSPECIFICATIONS246+w32BA5+w1ABABABABABAB0PhaseCycleBAw cycles(w>=0)requestor: MnRq _ FALSE;arbiter: MnGnt _ FALSE;4+warbiter: MnGnt _ TRUE;Figure 9. Timing for IOWriteFlowmaster: {MCmd _ IOWriteFlow; MAddr _ IOAddress; MnAdCycle _ FALSE}master: {MnAdCycle _ TRUE; MData _ IOData}slave: MnAdCycle=FALSE => MCmd#Done;slave: {MCmd _ Done; MAddr _ mumble; MnAdCycle _ FALSE}master: {MData _ IOData; MnRq _ TRUE} slave: MnAdCycle _ TRUE;FORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgE}.@eD w,A$-/[*$) *$)3IH4+1 w1dA$86d w5A$=: w:HA$A?H w>A$EC wC,A$JeH, wGA$ wLA$M Q"SD$"PD$QLN~=V;xOxJ}7~x0H} ~xF:BxA*x=V$x87x4r>r #*$.1GTVm$ COMMONMBUSSPECIFICATIONS256+w32BA5+w1ABABABABABAB0PhaseCycleBA(w>=0)w cycles4+warbiter: MnGnt _ FALSE;requestor: MnRq _ FALSE;arbiter: MnGnt _ TRUE;master: {MCmd _ IOReadFlow; MAddr _ IOAddress; MnAdCycle _ FALSE}master: MnAdCycle _ TRUE;slave: MnAdCycle _ FALSE => MCmd#Done;slave: {MCmd _ Done; MAddr _ mumble; MnAdCycle _ FALSE}Figure 10. Timing for MapRef and MapRefDirtymaster: {MnRq _TRUE; MnAdCycle _ TRUE}FORINTERNALXEROXUSEONLYqg}r {gg!Wq%gg'r(kgg)Pq*grg+ vgE}.@eD w,A$-/[*$) *$)3IH4+1 w1dA$86d w5A$=: w:HA$A?H w>A$EC wC,A$JeH, wGA$ wLA$M Q"SD$"PD$QLN~;=V}7~xJxOx0xF:AxAx=V&x9+7},~x4r&r #*$.1GTVm$ HELVETICA HELVETICA  MATH TIMESROMAN TIMESROMANY LOGO HELVETICAMATH HELVETICA HELVETICA HELVETICA HELVETICA TIMESROMAN TIMESROMAN TIMESROMANj X& 1 :sB K W c l t{cX j/k[]<>commonmbusspecs.tioga"Friday, March 22, 1985 9:18 pm PST