///CommonMBusSpecs.tiogaWrittenby:Sindhu,September1,19841:51:14pmPDTLastEditedby:Sindhu,March22,19859:17:20pmPSTLastEditedby:Barth,December13,19842:08:47pmPSTLastEditedby:McCreight,March22,19855:13:37pmPSTCOMMONMBUSSPECIFICATIONSTheCommonMBusDescriptionandSpecificationsDRAFTofMarch22,1985..nearlydone..Releaseas[Indigo]<Dragon>Documentation>CommonMBus>CommonMBusSpecs.tioga,.presscCopyright1985XeroxCorporation.Allrightsreserved.Abstract:ThismemoproposesacommonMbusforDragonandCworkstation.ItisintendedtobeusedbothasaconvenientsourceforinformationabouttheMbusandasareferencemanualforbusspecifications.ThememobeginswithabriefoverviewoftheMbus.Itthenlistsallthebussignalsanddefinesthemeaningofeachsignalgroup.Next,itusesthesesignalstodescribeindetailhowthebusoperatesatboththecycleandtransactionlevels,andhowcertaintransactionsareusedtomaintaincacheconsistency.Finally,itgivesthedetailedtimingofthebustransactionscurrentlydefined.XEROXXeroxCorporationPaloAltoResearchCenter3333CoyoteHillRoadPaloAlto,California94304ForInternalXeroxUseOnly���pï_,îâï]…îâîèî<î@î!Ýî#jî&°î+˜î-ãï[ÝîâîþîEî˜îœî"î$?î'…î,nî.¸ïZ6îâîþîEî˜îÉî#î%Tî(šî-ƒî/ÎïXîâîþîEî˜ îÁî$&î&cî)©î.’î0ÝqïVîâ�rîàïV�ïVî¼qîïV�ïVîè�rîÏïV�ïVîµ�qî(ïV�rïVîïsïMÏîâîšî Ï�î#ûtïHÙîâ îDî¶ ïCãîâî“îHî Pî$Wï@ÛîSî¾uï;åîâîeï;åî¢�vîï;å�ï;åîgð=ï:>îâwï5Hîâ�uï5HîÑî9îî†î#Ëî%„î(Óxï1ùîâvï1ùî¤îRî 5î'�î(Ûî/a�î1‚î4Íî7ˆî=<î@œ�ï0Rîâîfîîùî"nî$Šî&þî*ôî.³î1�î2© î:•î?Öï.ªîâ îžî»î6�îÔî!œî$zî&e�î' î.<î3cî5›î8cï)´îâîßîRîîF�î”î"ÿî)+î*óî-€�î/2î2ùî4Sî7²î:¹î<¸î?Fï( îâî îîqî#î%Rî'=î+î/„î5 î9î:xî>ï&fîâî(î3îîwî"¾î&6î)î,&î2Šî4Šî88î; î?0ï$¾îâ îµîWîcî!±î&Âî/Eî1÷î5³î7•î=¯ï#îâî£îîî#Þî&Ãî,·î1î3 î6†î9¹ï!pîâîyïÜîâvïÜî.¼î2ÿ ï5î.¼î2î5&î;Çïî.¼î2Yî7cî9íïæî.¼î2î5Š î<6tï Iîâîùî‘î"=î&Ï������� ��������TVm$é������������������������������COMMONMBUSSPECIFICATIONS2Contents1.Introduction2.BusSignals3.BusOperation4.BusTimingFORINTERNALXEROXUSEONLY���qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�zï^õîâ{ï[§î¤î0ïXXî¤î0îòïU î¤î0îòïQ»î¤î0îòrïî Ùî#î*$î.Ÿî1G��������k��������TVm$�_��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS31.IntroductionTheMbusisahighbandwidthsynchronousbusthatinterconnectsamultiprocessorsystem.FivekindsofdevicesconnecttoanMbus:caches,thatintermediatebetweenprocessorsandthebus,memories,someofwhichmaybemultiported,I/Odevicecontrollers,amap,responsibleforinformingthecachesaboutthecurrentvirtual-to-physicalmemoryaddressmapping,anarbiter,thatassignsmastershiptoatmostonerequestingdevice.ThisdocumentisthespecificationfortheMbusinterfaceofcaches.ItimpliesrestrictionsonotherdevicesthatconnecttotheMbusaswell,butitisnotintendedtospecifythosedeviceswithanycompleteness.MbuseshaveabriefbutinterestinghistorywithinXerox.Thecacheconsistencyprotocol,whichmanyconsidertobethekeyideathattheMbusimplements,firstoccurredtoDashiellofXeroxEDandThackerofXeroxPARCabout1980.TheoriginalintentionwasthatEDandPARCdevelopacompatibleMbusthatcouldbeusedbyPARC'sworkstationprojectsandED'sprinterprojects.Notenoughenergywasdevotedtoovercomingtheincreaseofentropy,andbysummerof1984EDnearlyhadaworkingMbusandPARChadapaperdesignofaratherdifferentMbus.SincethenithasbecomeclearthattheEDMbusasitexiststoday(weshallcallthattheESSMbus)willnotsatisfyallofED'srequirementsforitsplannedCworkstationline,andsoconsiderableeffortisbeingdevotedatEDandPARCtosettlingonacommondesignforthesecond-generationMbus.ThisdocumentisthefirstdetailedproposalfromPARCinthatdirection.ManyoftheapparentlyarbitrarychoicesinthefollowingsectionsaredictatedbyastrongdesirethatexistingESScachesfunctionaswellaspossibleonthenewcommonMbus.Theremainderofthedocumentgoesintogreaterdetailaboutthestructure,operation,andtimingoftheMbus.Thenextsectionliststhebussignalsindetailandgivesthemeaningofeachsignal.Section3nextusesthesesignaldefinitionstoexplainhowthebusoperates:itdiscussesarbitration,liststhesetofbuscommandscurrentlydefined,showshowthesecommandsareusedineachofthepossibletransactions,showshowtransactionsareusedtomaintaincacheconsistency,andintroduceshousekeepingoperationstodealwithaddressspaceswitchesandmultiportmemories.Finally,Section4discussesthetimingofarbitrationandofeachtransactionindetail.2.BusSignalsAnMbusconsistsofthreeindependentgroupsoflines.Thefirstistheclockinggroup.Thesecond,calledthearbitrationgroup,assignsbusmastership.Thethird,calledthetransfergroup,transportsdataoncemastershiphasbeenestablished.Thefollowingdescriptionusesthesenamingconventions:S[a..b)denotesagroupof(b-a)linesthatencodethebitsrepresentingthesignalS;mostsignificantbitsofthesignalarewrittenleftmost,andhavethesmallestnumericindex.Asignalrepresentedbyasinglewireiswrittenunencumberedwiththe[)notation.Allsignalsareassumedtofollowpositivelogicunlesstheyhavean"n"asthesecondFORINTERNALXEROXUSEONLY��qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�zï^õîâî¾qï[¦î¤î�îbî~îo�îî!Ëî), î1 î4½î8î@ô�ïYÿîâ îîrî —î$Kî&î*Íî/äî1’î3ƒ�î5]ïXîîî{î"uî'ã î.{î12î3’ïV#îî¦î9îòî#�î&î'õïT5îîÑîïRGî�î+î› î!Ëî%î,nî/Ëî5î9÷î=TïP î'î"gî'Ôî,¾ïN²îîõî¾îŒî! î(î)±î+Iî.¦î1Q î8�ïL6î¤î³îîwîÌî&¥î(Øî+-�î,üî/ˆî5#î6Òî;éî=VïJîâîÎîÅîTî î"Ìî'Óî)rî+Â�î-Œî0î1²î4èî7Yî8 î9üî<bïHèîâîî-îÌî•î °î#QïFlî¤�î[îøî�î"îQî ® î'Eî+³î/Õî4î7Bî:ë ïDÅîâî¯îÄî•î"î#Êî%Âî((î*Äî-Äî0™î2ÿ�î4àî7} î?FïCîâî¤îcîÖî î!Óî$nî'6î,Ÿî.hî2œî7î;î?FïAvîâîûîæî¡î~î"î$Þî)Rî.�î/Å î6ç�î8Ðî;uî>Rï?Ïîâîûî_î‚îë î#|î(Æî+¥î/4î3îî:;î=4ï>(îâî\îî=îë î$^î&¼î+ýî-µî3#î5Ùî7Ôî= î>Øï<€îâî^î}î&�îBîŠ�î Uî"Ýî%†î)Üî,…�î- î1sî5´î7^�î8yî<xï:Ùîâ�îÓîrî=îzîæîrî$žî(î*ëî-aî0�î1óî4Ÿî6dî7Ðî;›î?}ï92îâîîrî%îjîH�îî üî#Œî%æî)ùî+Îî-lî0¸î8ïî;î<Ðï7Šîâ�î^ îÂîËî}î;î'$î*éî,Oî0î5Fî6Ùî9_î<î@oï5ãîâîÁîÝ�îîãî!Hî#›î&î1q�î3aî6ÿî:/î@²ï4<îâî]îQî¥îZî"Ýî'^î)'î, î2ìî6þî8Óî;N ï2”îâîpî"î¹îî"üî(î*Bî/dî1H�î2[î6rî:\î=ï0íîâîÜî,î¦îTî Aî!ðî'1î)8î+—î.…î45�î6ï.rî¤î¦îiîLîÖî&nî)²î,µî1|î5rî9î< ï,Ëîâ îfîî{î6î —�î"sî%éî(Ãî+Õî0tî37î5™î81î<£î>Sï+#îâî¬î1î£îPîî"_î'Lî,?�î-†î0¨î3µî7Qî;O ï)|îâîoî!îîBî·î"}î#²î)Wî0Rî2óî51î7,î8Ãî;9ï'ÕîâîúîŒîÔî"î%Öî,öî/„î2úî4ãî8Oî:Bî<Üï&-îâîèî#îUî&î(…î+îî-Ëî3´î7®î?gï$†îâ înîê î$uî&î(×î+Ïî0–î4)î9jî;þï"ßîâîÁî(î!d�î"õî)î+Õî0Œî2¢ î9Ãî<×î>íï!7îâ îÞîŒzïšîâî¾î qïKî¤îÚ�î—îîóîî!û î)Îî.7î/Óî3°î6kî9&î:upî<·ïK�ïKî=Rqï£îâîµî‡îkî]pî!·ï£�ï£î"g qï£î(dî,¹î1Dî3Õ î;‹î>]ïüîâîÙpî9ïü�ïüî©qïüî3î î$îî'óî+: î2 î4•î7ñïî¤î®îô î"8î%dî) î.Gî7@ïî;¶î@ô�ïÙîâîïî³îî`î9î"öî%`î( î/ïî2Yî6Oî8î;† ï2îâîtîînîIîpî 1ï2�ï2î ”qî$Éï2�ï2î%–î(>î+upî-Åï2�ï2î.Iqï2î2Úî8.î<µ�î>3ï‹îâ î‚î³�îî2î!vî#î(�î1›î4ìî7€î9î?Ëï ãîâîbîÆîfî%î!nî&”î)öî.)î1Iî4 î6¡î9^î;î=Œrïî Ùî#î*$î.Ÿî1Gÿ������� b��������TVm$Â������������������������COMMONMBUSSPECIFICATIONS4characterofthesignalname.Someoftheselineshavepullupresistorstoensurethattheyremainunassertedduringcycleswhentheyarenotdriven.Theseresistorsdonotsupplyenoughcurrenttode-assertalineinonecycle;howevertheymustde-assertthelineinaminimumresetperiod.2.1ClockingGroupTheMbusistimedincyclesofatwo-phaseclock.ThephasesarenamedAandB,andaclockcyclebeginsattheleadingedgeofAandendsatthetrailingedgeofthefollowingB.AsignalthatconformstostandardMbustimingisdrivenontotheMbusassoonaspossibleafterthestartofphaseA,andissensedfromtheMbusbylatchesthatareopen(enabled)duringphaseB.ThismeansthatthelargestportionofaclockcycleisavailablefordatatopropagateandstabilizeontheMbus.AllofthefollowingsignalsexceptMPhAandMPhBconformtostandardMbustiming.MPhAThisisassertedduringthe"first"phaseofatwo-phaseclockcycle.MPhBThisisassertedduringthe"second"phaseofatwo-phaseclockcycle.MHoldThestateofthislineassampledattheendofcycleidetermineswhetherthestateoftheMbussystemattheendofcyclei+2istobeidenticaltoitsstateattheendofcyclei+1.MnResetThislineisheldassertedduringpower-up,andisassertedforatleast128consecutivecycleswheneveritisasserted.ThecyclefollowingthecycleinwhichMnResetisde-assertedisavalidMbuscycle.2.2ArbitrationGroupThearbitrationgroupconsistsofapairofrequest/grantlinesforeachbusrequestor,andoneothersharedlinecalledMnNewRQ.Asingle,centralarbitertime-multiplexesthetransfergroupamongseveralcontendingdevices.Eachofthesedevicesmakesrequeststothearbiterusingitsdedicatedrequestline,andthearbitergrantsmastershipofthebususingthededicatedgrantlines.Adevicethathasbeengrantedthebusiscalledbusmaster.Thesequenceofcyclesinitiatedbyamasterwilltypicallyinvolveatleastoneotherdeviceonthebus;suchadeviceiscalledaslave.MnRq[0..16)FORINTERNALXEROXUSEONLY���qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�qï_/îâîËî„îãîÎï\³î¤îuî*î°îçî!)î%Œî*Ôî,~î0àî3ªî6¶î;Y ï[îâîî¿î®îøî!†î$5î)Õî.î3˜î5Ùî8ˆî=4ïYeîâîÂî‡îN�îî\î! î#ãî'æî-€î0¦î4%î9ìî<bî?/î@ô�ïW½îâî7î~{ïTnîâîîäqïQî¤î‡�îmîî‡îî 9î$;î&��î'6î-Äî2Kî5/î9 î;ÿî@‘�ïOwîâî°îŒîZ�î›îFîÐî#6î$æî']î,Gî/¥î1u�î3î5çî9:î:êî=aïMÏîâîîÎî$î-îa�îäî#Æî&Šî,‰î.-î3¿�î5î8î<mî=ÏïL(îâî%î—�î„î-îîîGî î%\î(ªî+î.?î0î3ÿî5öî8Àî:?î>·ïJîâîB�îîµî²î:î î!^î$Ñî*òî/cî3Fî5î8ªî<ïî?¾ïHÙîâî/î�î¬�îÈîNî!´î#î(Àî*ðî-çî/ˆî5Üî8†î=Æî?¾ïG2îâ�îÂîAîšîZîÀî Øî%Nî)¥î.&î0ãî5Dî:Îî<ƒïE‹îâ�î¼îSpïB;îâqï>ìî¤î¾î)îaîÑî"1î&jî*Kî,�î-.î3°î7Dpï;œîâqï8Lî¤î¾î)îaîÑî"1î(#î,î-¾�î.èî5jî8þpï4ýîâqï1î¤î‰îÈîî>îî ¾î&:î'àî*Mî-î.Ùî2Z�î3O î:cî?¾ï0îâî$îîî_�îJîòî~î!(î#˜î&aî(+î+¯î.¹î06î1õî3÷î9˜î;Xî=Cî@…ï._îâîAîùî²î%pï+îâqï'¿î¤îùîëî’îèî"Zî'î-Ïî0Âî2iî7Ûî:Tî<(î?ˆï&îâ îJîTî œî"î#…î)¾î,ªî00î6Vî8Èî<Oî>ï$qîâîÊî5 îRî¾�îèî#O�î%)î'À{ï¥îâî î/qïVî¤î· î¶îóî%.î'"�î(‡î+špî-ŽïV�ïVî.qî1ªïV�pïVî2ZqïVî6-î9£î<î?‡ï¯îâ îpîIîî×î#^î&6î*Oî2ñ�î4 î9î=ïîâî5îyî iî$Pî(ºî-/ î41î9Ÿî<÷î>•ï`îâî pîÎï`�ï`îRqï`îçîŠî ßî%Eî(äî*³î0ßî5¨î8¬î;Yî=pï¹îâqï¹îð îÈîsîÅî Nî#éî&;î,cî/éî3ä�î5cî9šî<Zî>ÁïîâîíîXîúîqîspî!ï�ïî"+qïî&fî)Iî/<î1î5î:rî<y�î=®ïjîâî’îîòîî ºî#jî'î+Wî-bî/Æî2Úî6�î7?î;ˆî<øî@ô�pïÃîâqî°ïÃ�ïÃpïsîâ rïî Ùî#î*$î.Ÿî1Gÿ�������Ó��������TVm$•COMMONMBUSSPECIFICATIONS5Theselinesareusedbythecachestorequestbusmastership.Thereisadedicatedlinefromeachcachetothebusarbiter.MnGnt[0..16)TheselinesareusedbythearbitertosignalwhichofthecachesisthenextMbusgrantee.Liketherequestlines,theselinesarealsodedicated,onepercache.Thereisapossibilitythattheywillbereplacedby4encodedgrantlinesthatsupplythenumberofthecachetowhichthebushasbeengranted.Alternatively,theseencodedlinesmayberuninadditiontothedecodedlines.TheencodedlinesareneededbytheMapprocessortofigureoutwhichprocessoriscurrentlybusmaster.MnNewRqThislineislogicallyunnecessary,butcanreducethevarianceinMbuslatency.Thislinesignalsthatthecurrentgranteewantstoretainhisgrant,butiswillingtorelinquishitifthereareotherrequestersatthistime.Thislinehasapullupresistor.2.3TransportGroupThetransfergroupconsistsofapproximately42wires.MnAdCycleThislineisassertedlowduringcycleswhenavalidcommandisbeingassertedonMCmd.Thislinemaybeassertedeitherbythemasterofthecurrenttransactionorbytheslaveselectedbythefirstcycleofthecurrenttransaction.MTransport[0..36)Thesethirty-sixwiresareusedtoencodethreefields:MCmd[0..4),MAddr[0..32),andMData[0..32).Sincethisaddsuptomorethanthirty-sixwires,thesefieldsaretime-multiplexed.ThesomewhatpeculiarwayinwhichthismultiplexingisdoneallowstheESScachetoattachtothirty-twoofthem,MTransport[5..36).MCmd[0..4)=MTransport[4..8)ThisfieldisonlyvalidifMnAdCycleisasserted.ItencodestheMbuscommand,whichspecifiestheactionduringthecurrentbuscycle,andmaycarryimplicationsforfuturecyclesaswell(seetransactions,section3.3).ItisassertedbythesamedevicethatisassertingMnAdCycle.ThecommandscurrentlydefinedarediscussedlaterinSection3.2.MAddr[0..32)=MTransport[0..4)|MTransport[8..36)ThisfieldisonlyvalidifMnAdCycleisasserted.ItsinterpretationdependsonMCmd,whichisadisjointfield.Thisfieldnormallycarriesanaddress.MData[0..32)=MTransport[4..36)ThisfieldisonlyvalidifMnAdCycleisde-asserted.ItsinterpretationdependsonpreviousvaluesofMCmd.Thisfieldnormallycarriesdata.FORINTERNALXEROXUSEONLY��qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�qï_/î¤îçîcî÷îuî!±î$Rî(ãî*Óî/éî2À î;î?Gî@ô�ï]ˆîâîîÏî6îgî"3î#áî&Aî(×pïZ8îâqïVèî¤î§îäî9îwî uî"Öî'Hî(ùî,æî0õî2°î5î9dî:Ñî=2î@D�ïU@îâîîwî½î3î"î%Èî)hî,ºî/$î2 î8¬î;oî=úïS™îâîÚî<�î\ îÔî˜î!žî$?î&&î+¡î-“�î.¾î4.î7·î:èî=ïQòîâîZîŸîqîéîÎî •î$¼î'4î)ãî,qî/çî5ô î>•ïPJîâîbî¤î®î¥îBî öî&kî( î*†î0î4*î7 î<‰î?ÊïN£îâî§îŸîûî>î!Nî"øî&öî)hî-rî3‚î4êî:Ãî=VpïKSîâqïHî¤î±îZî¹îî&î(zî*øî/hî1ºî7î8½�î:Šî=ïF\îâîîÁî8î îtî#Dî(*î,î-Èî1»î3õî7èî:pî;ãî@oïDµîâ îGî‹îÚîQî’î! î'î)î+¦î/ƒî2‹î5/î7’�î8ªî<þ{ïAeîâîî€qï>î¤î|î‡î‰î"‰î$Bî-Cî/(pï:Åîâqï7uî¤î¼îqîÛîî ¯î%î)î,Ç�î-ïî1Tî7³î9î<çï5Îîâî×îYîbîîúî Úî&�î)Ûî+Æî.î2sî4î6jî;" ï4&îâî¦î¢îîhî•îî!ðî$Èî(;î)ôî,Sî1pï0Öîâqï-†î¤î~ î(î”î Àî#Ôî%[î)çî-Hî1O î94ï+ßîâî™îÄîzî!î$Wî&iî(î+ªî.Ð î4¢î8î<î?Êï*8îâî î‘î$î)qî,bî.)î2Oî5 î='î>«ï(îâîîoîhî4îãî!ñî# î*î+ºî/œï%Aîâ î—�î|ï"Åî¤î î…î=î¢î!Uî#î+î,Æî3pî53î:¶î=b�î?‡ï!îâî·îáîvî!òî&&î*³î-.î2î4Æî8î;€î> ïvîâî’îÉîçî Øî"€î%gî(.î0�î4–î8î9Œî:ñî@"ïÏîâî;î±îïî·îî"º î+Jî.î4úî:Ñî?Êï'îâîìîî¿îžï×îâîs�îXð"ï[î¤îÓîî3îbî Þî"Tî*+î+¬î1éî3ú î<¯ï´îâîèî îîƒ�î¬î!–î%¢î(¼î+ìî1½î6î8ïdîâî2�îïèî¤î·îáîFîZîºî!î(Ðî*5î2!î4 î<¯ï Aîâîèîwî¥î^î"î%î(Mî.î2wrïî Ùî#î*$î.Ÿî1Gÿ�������È��������TVm$m������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS6MParityThislinecarriestheparityofMTransport.TheparityisoddanddrivenonecyclelaterbythedevicethatdroveMTransport.MnSharedThislineindicatesthatacopyoftheaddressedmemorywordispresentinaslavecache.Thislinehasapullupresistor.MnAbortThislinepreventsmemoryfromrespondingtoaReadQuadandallowsacachetorespondinstead.Thiswireisnotlogicallynecessarytothecacheconsistencyprotocol,butitallowsaperformanceoptimization.Thislinehasapullupresistor.MnHousekeepingInProgressFollowinganycycleinwhichthislineisnotasserted,everycachethatisdoinghousekeepingassertsit.Followinganycycleinwhichitisasserted,everycacheactivelyde-assertsit.Twounassertedcyclesinsuccessionmeanthatnohousekeepingisinprogress.Thislinehasapullupresistor.MnErrorThislineisusedtosignalabuserror.Theonlybuserrorcurrentlydefinedisbusparityerror.Thislinehasapullupresistor.3.BusOperationMbusoperationisspecifiedattwolevels:cyclesandtransactions.Asexplainedearlier,acycleisonecompleteperiodofthesystem-widetwo-phaseclock.Atransactionisasequenceofcontiguouscyclesinitiatedbysomebusmaster.Duringthefirstcycleofeverytransaction,MnAdCycleisasserted,MCmdspecifiesthetransactiontype,andMAddrspecifiesanaddress,whoseinterpretationvarieswithtransactiontype.Subsequentcyclestransferdata,performothermanipulations,orsignaltheendofthetransaction.Recallthatthedevicethatinitiatesatransactioniscalledthebusmaster,andotherdeviceswithwhichitinteractsarecalledslaves.Busmastershipisgrantedbythearbiter.Thusoverallbusoperationisasimplepipelinedcyclicprocessofarbitrationfollowedbytransactionexecution.Thedescriptionbelowfirsttakesuparbitration.ItthendescribesthevariousMbuscommandsaswellasthesetoftransactionsthatusethesecommands.Forcompleteness,italsodiscusseshowcachesmaintainconsistencyofmultiplecopiesofshareddata.Finallyitdiscussesasetofhousekeepingoperationsthatdealwiththemappingproblemsintroducedbymovingaprocessorfromoneaddressspacetoanother,andwiththeconsistencyproblemsintroducedbymultiportmemories.ThedetailedtimingofarbitrationandofeachofthetransactionsisnottakenupherebutislefttoSection4.3.1ArbitrationFORINTERNALXEROXUSEONLY��qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�pï_:îâqï[ëî¤îÐî˜îîvî"€î$K î,öî/áî3êî5hî8Gî;î?rïZDîâîUîzîvîÖîî èî$É pïVõîâqïS¦î¤îÔî îgî K�î!‹î$òî&Áî)7î/£î5&î8Åî:Fî?0î@ô�ïQÿîâîIîñîîÁî6�î `î$ÇpïN°îâqïKbî¤îµîdîàî"Eî%£ î,·î.]�î/î6]î9î=1�î>RïIºîâî»î'î îOî"ˆî$î&½î,Uî2’î4kî6õî:ë ïHîâî¨î)î€î�î× î%Ûî.¯î1Êî4€î6õ�î8î<…pïDÄîâqïAvî¤î î½î,îÕî#ßî&}î)/î*—î-î2“î6Cî:î<Õî>=ï?Îîâî¬î&î®î%Zî(%î+Ãî-î1Öî3Wî4îpî:¨ï?Î�ï?Îî;Cqï?Îî>Rï>'îâîÁ îÖîÇîË î%pî)Gî*Ô î1Lî4ìî7™î9ï<€îâîNîüîEî_îî ‹�î!µî&pï91îâqï5âî¤î¿îwîäî"îÑî!¾�î"éî%î)Òî,«î/Çî2_î5Òî;°î@²ï4;îâîyîpî¾îØîŽî"�î#-î'“zï-žîâî¾î qï*Oî¤�îgîæîùîNî"òî$tî' î+6î/î1¶î9äî;Þï(§îâî¿�î*îÞî‹îxî#¢î(=î*8î,Ø î4Ûî;Ÿî@‘�pï'�îâ qï'�îÒî4�îUî4îã î&Ëî*¸î0î2î5î8î=Uï%Yîâîzî‹î7î)îî%£î-žî/Bî5î:î?¾ï#±îâ îïîhî1î!7î&Áî(Ãî.î2V î;î?ï" îâ îìîó î!mî%rî*Šî-õî3[î7 î@Zï cîâî×î@îîÄî.î$î(\î+4î-î1ìî4Äî9î�î;" ï»îâîVîVî½î\î-î íî$”î)eî,‰î0Ÿî1ýî7€î9Ûî=Ûïîâîº îÁîMînî!‹î$î)šî-9î1ßî4—î:áî<n�î=¹ïmîâîöîÂî•îN î&î+¸î-³ î4¯ ïòî¤î î°îÎî"·î&Fî(jî0,î1µî4ìî:åî=VïJîâ�îÈîjî[îîî Çî#2î%[î'î.«î1…î4î7šî?rï£îâî°îîî!äî%î)kî/? î6‹î8]î=ðïüîâî î îôîªîî$Ð�î%þî(î)Ýî2€ î92î<î?ïTîâî9îìîì î#Õî%Èî*³�î+Õî1àî5>î7áî<Ãî@oïîâî7îàîìî= î#bî)\ î0?î2,î8=î?Fïîâî/îžîl î!Eî$î%ßî)%î*óî-hî4ýî6}î9î<Üî?ï ^îâîcîÏîDîòîÒ{ï îâî rïî Ùî#î*$î.Ÿî1G�������*��������TVm$’��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS7ThesignalsinvolvedinarbitrationaretheMnRq-MnGntpairsrunningtoandfromeachpotentialmasterandthearbiter,andasinglelineMnNewRqusedtoincreasethefairnessofarbitration.Adevicerequeststhebusbyassertingitsrequestline.IfoneormoreMnRqlinesareasserted,andthereisnomaster(grantee)atthemoment,thearbiterperformsagrantcycleinwhichitissuesthebusbyassertingMnGntforadevicethathasMnRqasserted.ThebusmasterkeepsMnRqassertedwhileitstillwantsthebus,andthearbiterinturnkeepsthatmaster'sMnGntasserted.Ifthemasterisexecutingalongsequenceofcyclesthatisnotrequiredtobeatomicwithrespecttootherdevices,itmayassertMnNewRqtoindicateitswillingnesstogiveupthebusifthereareotherrequestspending(forcorrectoperation,MnNewRqmustbeassertedonlybythecurrentmaster).MnNewRqcausesthearbitertodoagrantcycleeventhoughthecurrentmasterstillhasMnRqasserted.Thisstrategypreventsamasterfromhoggingthebus(unless,foratomicity,itneedsto).Atthesametime,itavoidswastingcyclesinthecasethatnodevicesarewaitingtogetthebus.Asolutioninwhichthemasterreleasesandreacquiresthebus,forexample,doeswastecyclesinthiscase.3.2MBusTransactionsTherearecurrentlyninemastertransactions:ReadQuad,WriteQuad,WriteSingle,MapRef,MapRefDirty,IORead,IOWrite,IOReadFlow,andIOWriteFlow.Thebusmasterinitiatesamastertransactionbyassertingtheappropriatecommandwithanaddressofsomekind.ThiscommandandaddressisinterpretedbyeverydeviceattachedtotheMbus,andoneormoredevicesdecidetoactasslavesduringtheremainderofthetransaction.Somemastertransactionsconsistofafixedsequenceofcycles:WriteSingle,IORead,andIOWrite.Othersareflow-controlledbytheMnDVline:ReadQuadandWriteQuad.Theremainderareflow-controlledbytheslavetransactionDone.Flow-controlledmastertransactionsbeginwithafixedsequenceofcycles,dependingonthetransaction,waitfortheirflow-controllingevent,andthenterminateinafixedsequenceofcycles,againdependingonthetransaction.Flow-controlledtransactionsmustselectexactlyoneslave.TheMbusspecificationincludesmeansfordetectingwhenthisisnotso.(Ohyeah?Howdowedothis?WhateveriseasiestforEDshouldprobablyprevail.)Transactionsthatareflow-controlledbyDonemaycontainsubtransactionsthatarenotflow-controlledbyDone.Duringthosesubtransactions,theslaveofthemaintransactionactsasmasterofthesubtransaction.IOdevicesmayrespondtoanyorallofthefourIOtransactions.MbuscommandsarecarriedintheMCmdfieldandarevalidwhenMnAdCycleisasserted.Twelveofthesearecurrentlydefined,andtheotherfourarereservedforfutureuse.Inthedescriptionbelow,thedecimalnumberincurlybracketsafterthecommandnameindicatestheencodingofthecommand.(Onpage8ofthe21Jan84ESScachespecification,thereare(optional?)waitcyclesappearingbeforeseveraltransactions.Whatdoesthismean?)ReadQuad{0or2(sigh!)}ThiscommandisissuedbythemasterduringthefirstcycleofaReadQuadtransaction,whichreadsaquadintothemasterfrommemoryorfromanothercache.FORINTERNALXEROXUSEONLY���qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�qï_/î¤î~îïî‹î ; î'î)Vî+¸ î5î8}î=¶î?gï]ˆîâîoîÇî©î @î#î%¤î*“î-q�î.Áî2Óî5°î= î@oï[àîâîîXîBîåî$[�î%Òî*î/Dî1Žî4î5õî;„î=IïZ9îâî–î(îäî¹î]î Þî$)î&î,.î.õî2î4î6"î:£î@…ïX’îâî+îÛî$î~î#D�î$Wî'Õî+1î,Éî0Àî2�î5Êî8î:”î<yïVêîâîâî�îIîî\î Ñî%AïToî¤îdîäî=îüî#Uî(uî,î-Qî/Ûî3¥î5íî8Åî;eî=ïRÈîâîÍîî#î.î ¸î%õî,ƒî.Bî0ßî5Œî75î=�î?ïQ îâîÆî{înî8î î!î&œî(Gî*3î.«î1Áî6fî8î;«î@ÈïOyîâîÕîîµîSî#oî%9 î,"î-Àî0î2Ÿî4íî7sî8Ãî<<î>ïMÒîâî^îÚî´î!i î(î/hî2ôî5î:bî=Ÿî?¾ïL*îâî¯î{î ´î$ñî'Tî+Èî-zî/„�î0±î4Hî7¾î;î?¾ïJƒîâîîßîaî·î! î&ßî)Úî.Ñî47�î5Bî9”î<ÜïHÜîâî,îîŒî´ î ôî"5î&î(Ùî*¿î- î0pî3Øî5î9Gî>'ïG4îâîºîCî\îTî„î wî"ôî'òî)Êî,=î.Æî2Œ�î4Cî9¯î;‡î?¾ïEîâîRî\î î!¡î$î&ïî)-pî.þïE�ïEî/®qïEî2î5Âî9¹î;gî> {ïB>îâî�îîÆqï>ïî¤î‚î±î kî$aî)®î2„î:ž ï=HîâîÙîhî)î/sî6 î?gï;¡îâîî?î9î$î)“�î+!î/õ î7Uî9µî?¾ï9ùîâ î:î•î¨î!’î&uî('î+³î/±î2Åî9î;Ïî@²ï8Rîâ îõîñî¥îêî%fî'î)t�î+Oî.>î0öî3¢î5fî8ùî=Ãï6«îâîîÄîrî]îÎî-î%Åî'~î)Ýï4/î¤îªîJî!ûî&§î(�î)êî-˜î3±î5šî:;ï2ˆîâîŠîZîáî"uî$áî.‹î0 î3î7ïî;8ï0áîâî î²î‘î#/î%Šî/"î1$î3‹î6ù î=ûï/9îâîÈî î$ˆî(:î+<�î,Mî/²î5‚î7"î;Yï-’îâîî¡î"îHî ²î$&î.Rî2‹î5pî8Âî?î@ô�ï+ëîâî`îHîîPî!úî(¿î*Åî-$ï)pî¤î"î$#î( î,Kî1gî4“î9Õî=-�î?‡ï'ÈîâîÊî3î {î"½î(ªî,dî/ î0{î2ôrî6&ï'È�ï'Èî6‡î8pî;óî>¨î@Jï&!îâîøîÝîSîíî×î"î$˜î(¥î-Äqï&!î3Úî<gî?Êï$zîâîaîKîî õî%Âî/Cî1ÿî4@î6£î@"ï"Òîâîdîî¨î%î'Îî+#î,Êî/î2‚ î9lî<î=®ï!+îâî›îúï°î¤îÀî‰îŒî Ïî"}î%î&âî(Òî*‹î,êî/îî2 ï4î¤�î\îÐî“îÅî#?î$Ëî' î+¯î.¾î1Sî3„î6Éî:\ïîâîYî„îWîî ±î#î(ùî.]î1 î3‹î76î:Fî<¥ïæîâîî.îjî.îƒ î#‹î'åî*:î/Qî4rî6î9‰î>âï>îâîAî¢îbî!î#sî)Zî+î-srïÃî¤îÿî²�î¾î4î/îÈîæî î"õî& î,¿î/¨î1™ î72î9¨î<éïîâîUîüî«î¬î"9î$TpïÍîâî‘îvî/�îcqï~î¤îàîdîòî!8î#Vî%Øî*kî.þî1€î4{î8î9ì�î;8ï ×îâîîî˜�î©î"î$Îî'î+lî.ºî4î5ºî9î=úrïî Ùî#î*$î.Ÿî1G���������������TVm$Ú����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS8Aquadisfourcontiguous32-bitwordsalignedinphysicaladdressspacesuchthattheaddressofthefirstwordis0MOD4.DuringthisfirstcycleMAddristhephysicaladdressofoneofthewordsinthequad.ThetransactionthenconsistsofzeroormorewaitcyclesuntiltheMnDVlinesignalsthatthememorysystemisresponding.TheaddressedwordwillbeassertedonMDatabytheslaveduringthatcycle.TheremainingwordsofthequadwillbeassertedonMDatabytheslaveinsubsequentcyclesinanorderdeterminedbytheiraddressMOD4:AddrTransportorder0=>{0,1,2,3}1=>{1,0,3,2}2=>{2,3,0,1}3=>{3,2,1,0}Cachesbuilttothisspecificationwillunderstandboth0and2asencodesforReadQuad,butwillissueonly0.WriteQuad{1or3((sigh!)}ThiscommandisissuedbythemasterduringthefirstcycleofaWriteQuadtransaction,whichwritesaquadfromthemastertomemoryandtoothercaches.InthefirstcycleMAddrcarriestheaddressofthequadwhich,unliketheaddressforaReadQuadtransaction,mustbe0MOD4.InsubsequentcyclesthemasterassertsthedataofthequadonMData,inorderofincreasingaddress.ThemasterreleasesMnRqforthistransactioninthecycleafterMnDVisassertedbytheslave.Cachesbuilttothisspecificationwillunderstandboth1and3asencodesforWriteQuad,butwillissueonly1.WriteSingle{7}ThiscommandisusedbythemasterduringthefirstcycleofaWriteSingletransaction,whichwritesasinglewordintothephysicaladdressspace.WriteSingleneverwritesthewordtomemory,butonlytocachesthatalreadyholdacopyofthequadcontainingthewordbeingwritten.MAddrcarriesthephysicaladdressofthewordinthefirstcycleofthetransaction.Thedataisassertedbythemasterinthenextcycleofthetransaction.MapRef{12}Thiscommandisusedbythemasterduringthefirstcycleofavirtual-to-physicalpagetranslationtransaction.Useofthistransactionindicatesthatthemasterintendstoreaddatainthereferencedpageofitsvirtualaddressspace(eachmastermaybeoperatinginadifferentvirtualaddressspace).InthatfirstcycleMAddr[7..32)containsavirtual512-byte-pagenumber.Thefinalcycleofthetransactionisthecycleinwhichtheslave(map)assertsaDonecommandthatcontainstheresultsofthetranslationinMAddr.(DoestheESScachereallyrequirethreedeadcyclesaftertheDone?Isthatbecauseitsmatcheristiedup?)FORINTERNALXEROXUSEONLY��qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�qï_/îâ�pîyï_/�ï_/î*qï_/îÖîLî[ îWî#Yî'pî,Nî.î3_î8Tî<î?Pï]ˆîâînî…îkîøîýî!²î#K�rî$¬ï]ˆ�ï]ˆî%¾qï]ˆî(1î*›î/‘î2_î5dî9î>&î?¾ï[àîâî/îîÒî~î7î!—î%£î'Qî)±ïYeî¤îƒ î‡î´î#¼î%|î(‡î*Sî-íî0îî4íî8;î:¢î?gïW½îâîMîîrîÛî"Rî#º î+©î.}î4Ïî8Sî:úî<çïVîâîâîŽî„îÝî=î!¨î$oî(±î+ƒî1þî6î7·î:î=ˆî@-ïToîâîîöî”î{îÅî"î#± î*Åî.§î0Aî2î5¼ î<ðî>×ïRÇîârîÌïRÇ�ïRÇîÝqïRÇî$ïPLî¤îSî©ïMÐî¤�îØînî«î8îÅïKTî¤�îØînî«î8îÅïHØî¤�îØînî«î8îÅïF]î¤�îØînî«î8îÅïCáî¤îjîÄî†î:î&1î(ð î0+î3{�î4Ãî7�î8Õî:–î?áïB:îâî î¡îMî©î!Ãpï>êîâîëîÐî‰�î½qï;šî¤îÛîZîãî!$î#=î%ºî*Gî.Öî1Rî4Hî7Ùî9¯�î:öï9óîâîNîsîŒ�îÍî#cî&âî)Yî-áî/¦î5+î7úî9Àî=vï8Lîâî½î)î îŒîî"óî%_î*Uî,î.†î2î6ƒî:Èî=4ï6¤îâîB�îŽî—î!î$™î&¬�rî(ï6¤�ï6¤î)qï6¤î+~î-Ôî/Æ î7î;+î=®ï4ýîâî5î™î¢î_îÃî Fî"Pî'`î)î,Ëî.ˆ î5î:Ñî=®ï3VîâîæîQî‰î% î$î%Ãî(î+Šî.Àî3xî4Þî:î<î>_ï/3î¤îjîÄî†î:î&1î(ð î0+î3{�î4Ãî7�î8Õî:–î?áï-‹îâ îbîãîŽîëî"pï*<îâ îfqï&ìî¤îåînîî eî"ˆî%î)§î.@î0Çî3Çî7aî9B�î:“ ï%Eîâî/î7î2�îUî#9î&»î)î+æî1,î6î:“ ï#îâîÅîàîXîùîÁî$Ÿî'9î*kî,2î0›î3‚î8nî;¸�î<úî@eï!öîâî=î· îlîÆî!Jî%î*–î/†î3Üî67î;î@eï OîâîCîÌî{îÜîµî)î ãî#Cî+î-öî0üî2iî7¡î9žî;þî@pï§îâîAîQîÄî}îÜpïXîâî#qïî¤îœîÜî&îAî!î#Yî'¨î+÷î.5î0ìî4>î5Õ�î6Ýïaîâî îÅî uî#/î$Ôî'a î.Jî3çî6¡î8íî=JïºîâîŒî¡î¢îKî¦ î!eî$§î&[î(1î,‡î1lî5î8Âî=.î@-ïîâî=î(�îŽîpî#î(.î-²î/½î2Èî5Ýî9ïkîâî[�î›îî"÷î)+î,î/^î2çî4¶î7+ î>=î?¾ïÄîâîUîîîoîÖî!âî&1�î'[î+%î1†î4Tî9·î<î@eïîâîU î-îîrîNï�ïî¯î"’î$ˆî&øî*î-)î1 î3ñî6±î9íî<“î>ˆïuîâî î^îyîõî3îVî‹ïî Ùî#î*$î.Ÿî1G�������*��������TVm$#��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS9MapRefDirty{10}Thiscommandisusedbythemasterduringthefirstcycleofavirtual-to-physicalpagetranslationtransaction.Useofthistransactionindicatesthatthemasterintendstowritedatainthereferencedpageofitsvirtualaddressspace(eachmastermaybeoperatinginadifferentvirtualaddressspace).InthatfirstcycleMAddr[7..32)containsavirtual512-byte-pagenumber.Thefinalcycleofthetransactionisthecycleinwhichtheslave(map)assertsaDonecommandthatcontainstheresultsofthetranslationinMAddr.IORead{4}ThiscommandisusedbyamasterduringthefirstcycleofanIOReadtransaction.MAddrcontainstheIOregisteraddress.Thesecondandthirdcyclesareidle.AnynumberofdevicesmaygeneratesideeffectsinresponsetoanIORead,butexactlyoneslavemustassertdataonMDataduringthefourthcycle.TheinterpretationofanIOReadisentirelyuptotherespondingdevice.Thusitmayactuallyreadfromarealdeviceormaycausesomesideeffect,orboth.IOWrite{5}ThiscommandisusedbyamasterduringthefirstcycleofanIOWritetransaction.MAddrcontainstheIOregisteraddress.ThemasterassertsthedataonMDatainthenextcycle.Anynumberofslavesmayrespond,buttheydosoundetectedbytheIOWriteprotocol.IOReadFlow{8}ThiscommandisusedbyamasterduringthefirstcycleofanIOReadFlowtransaction.MAddrcontainstheIOregisteraddress.TheslavesignifiesreadinessbyaDonecommand,andassertsdataonMDatainthefollowingcycle.IOWriteFlow{9}ThiscommandisusedbyamasterduringthefirstcycleofanIOWriteFlowtransaction.MAddrcontainstheIOaddress.DuringthesecondcyclethemasterassertsdataonMData.InsomesubsequentcycletheslavesignifiesreadinessbyaDonecommand,andthemasterre-assertsthesamedataonMDatainthefollowingcycle.Done{14}Thiscommandisissuedbytheslavedevicetoflow-controlaMapRef,MapRefDirty,IOReadFlow,orIOWriteFlowtransaction.ThevaluethatitassertsonMAddrdependsonthetransactionandtheslave.IfthetransactionisMapReforMapRefDirty,thentheslaveisthemap.MAddr[0..25)containsthenumberofthe512-bytephysicalpagecorrespondingtothevirtualpagethatinitiatedthetransaction.MAddr[25..28)carriesoneofthefollowingorders:NoClear{7}--noactionrequiredFORINTERNALXEROXUSEONLY��qïgîà�rî Þïg�ïgî!ºqî&ïg�ïgî'æ�rî(Îïg�ïgî)³�qî+&ïg�rïgî+ívïgîEÉ�pï_,îâ î3qï[Ýî¤îœîÜî&îAî!î#Yî'¨î+÷î.5î0ìî4>î5Õ�î6ÝïZ6îâî îÅî uî#/î$Ôî'a î.Jî3çî6¡î8íî=JïXŽîâî…î÷îñî”îè î!¡î$Üî&Šî(Yî,¨î1‡î51î8Ðî=5î@-ïVçîâî=î(�îŽîpî#î(.î-²î/½î2Èî5Ýî9ïU@îâî[�î›îî"÷î)+î,î/^î2çî4¶î7+ î>=î?¾ïS˜îâîUîîîoîÖî!âî&1�î'[î+%î1†î4Tî9·î<î@eïQñîâîA îî´pïN¢îâîqïKSî¤îîÛî¤î!>î#˜�î% î)îî.½î1zî4±î8‚î:™î<çïI¬îâîÊîÇî!3î#šî%¿î*¥î0|î3\î7öî:¶î>'ïHîâîîyîbîtîî"Áî%ªî+î-Ñî2î3šî9%î:¹î<ïF]îâîcî�î«îî{î#Eî&Jî(Qî-î1tî3Ôî8ïCâî¤îy îîÌî ¹î%îî'Wî,Sî.cî0î2k î9…î> ïB;îâî8î<îSîmîÔ�îþî"´î&ùî(½î+Áî/vî3 î5áî:î;Épï>ìîâîhqï;î¤îîÑî•î!*î#�î%î)Ëî.”î1Mî4~î8Jî:\î<¥ï9öîâîßîæî!\î#Îî%üî*íî0Øî3Âî8Eî<§î?ï8NîâîýîÄî‡îûîî!—î$¯î)ðî+¾î/½î2Öî8…î;î>?î@Zï6§îâ îëîæîFî¾pï3Xîâ îåqï0 î¤îàîdîòî Qî"o�î#¼î(Oî,âî/dî2_î5õî7Ðî9ã ï.bîâîÌîÊî!7î#Ÿî%Åî*¬î0…î3fî6Öî<,ï,ºîâîÞ�îîÒî‹îCî#’î&—î(î-Pî.þî1^î7ppï)kîâ î?qï&î¤îÛîZîãî =î"V�î#î(+î,ºî/7î2-î5½î7”î9¢ ï$uîâîÙîÞî!Qî#Àî%ìî+Òî0ªî3î7»î;>î=®ï"Îîâî4î<îEîÚî¬î#B î*oî-åî0Gî3±î9�î>õî@ô�ï!'îâî£îSîîWî"½ î(¦î*üî.pî1kî3hî8î9¶î<ïîâpï0îâî„qïáî¤î3î îêî"ƒî$óî'Èî+¤î0^î2‚î:¸�î<Wï:îâîà î „î"Z î*çî2âî5Ìî9‡î<gî=Ïï“îâîèîÝîLîRî² î&î)eî+Äïî¤îyî, î{î:î$üî'î0Sî3Íî6î::î;ùî>¬ïpîâîˆî�îtî$µî&ƒî(÷î.¦î4 î7dî@oïÉîâîAîœîâî±î!î#tï Nî¤îåî?î!ëî#¤î&î,ï Òî¤î6îËîBîIî!arïî Ùî#î*$î.Ÿî1G�������ê��������TVm$—��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS10ClearRPDirty{6}--writepermissionforthecurrentphysicalpageissummarilycancelledinallcaches.Fromthispointon,anycachewishingtowritetoavirtualaddresslyinginthisphysicalpagemustacquirenewpermissionviaMapRefDirty.ClearVPValid{4}--virtualmappingstothecurrentphysicalpagearesummarilycancelledinallcaches.Fromthispointon,anycachewishingtoreferencethisphysicalpagemustacquireanewvirtual-physicallinkageviaMapReforMapRefDirty.WriteProtectFault{2}--aMapRefDirtyfailedtoacquirewritepermissionfromtheslave.ThisorderisofinterestonlytotheMbusmaster.PageFault{1}--theslavefailedtolocateavalidvirtual-to-physicalmapping.ThisorderisofinterestonlytotheMbusmaster.MAddr[28..32)carriesagroupoffourflagsfromwhichthemastercacheshouldupdateitsmappinginformation(exceptifthereisaPageFault):MAddr[28]--reservedMAddr[29]--writeprotect(=NOTdirty)MAddr[30]--dirtyMAddr[31]--referenced(=true)(Note:Theseflagsareallredundant.Theycanbeinferredfromthetransactionanditsfaults.TheyareincludedforbackwardscompatabilitywiththeESScache.)IfthetransactionisIOReadFloworIOWriteFlow,andtheslaveisnaive(ignorantofmapping),duringtheDonecyclethefieldMAddr[25..28)carriestheorderNoClear.IOdataisthentransportedinthefollowingMbuscycle.IfthetransactionisIOReadFloworIOWriteFlow,andtheslaveissophisticated(awareofmapping,probablythemapitself),thenMAddr[0..25)cancontainthenumberofa512-bytephysicalpage,andMAddr[25..28)cancontaintheordersNoClear,ClearRPDirty,orClearVPValid.IOdataisthentransportedinthefollowingMbuscycle(eventhoughthatdatamaybemeaningless;theIOReadFloworIOWriteFlowmayhavebeenexecutedforthesideeffectsofitsDonecommand).Infact,themapwillprobablycontaina"Donereflector"IOregister,thatwillsimplysavethedatasentbythemasterinanIOWriteFlowtransactionandretransmititintheappropriatefieldsoftheDonecommandthatterminatesthetransaction.Reserved{6,11,13,15}Thesecommandsarereservedforfutureuse.Cachesbuilttothisspecificationwillignorethem.3.3TheCacheConsistencyProtocolThecacheconsistencyproblemistopreventmultiplecopiesofadatumindistinctcachesfromhavingdifferentvalues.ThisproblemarisesbecauseDragoncachescontainshareddatathatmaybewritteninto.ThesolutioninvolvestheuseoftheMnSharedandMnAbortbuslinesandtwoadditionalbitssharedandownerstoredwitheachquadinacache.ForagivenFORINTERNALXEROXUSEONLY���qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîEqï_'î¤îDîÅî(î!’ î(mî*–î,âî1—î6Ðî:î;Zï]îâîãî”î†î·î!î$3î'Õî*6î,Ùî0¨î5µî7fî:æî<—�î=Ãï[ØîâîÌî>îìîî Ûî$!î'Šî,iî/W î6Gî8„ïY]î¤î7î¬îî"=î(]î)ëî,*î0Ôî6î9'î;ZïWµîâî îàîùîvî"tî%>î)î+î.Wî2Lî7î9Vî?|ïVîâîÕîÁîÎî"R�î$!î'µî1÷î7dî:Fî@ZïTgîâïQìî¤îÆîIî �î!Ä î*Eî.î/£î4pî7Ú î>·ïPDîâîAî„îžîSî¿îxî$Wî'qî)î+~�î-Yî/ïïMÉî¤î-îÖî`îÒî"Lî&5î'öî,��î-=î0·î<ïL"îâîüî±îîÕî´î Îî"}î$Ü�î&¶î)MïI§î¤îÔî�î 4î$%î%Íî(¿î+éî/>î3;î5‰î9çî=¢ïGÿîâîuîOî î"•î'_î(¿î,Iî-´�î.Þ ïE„î¤î¿î6ïC î¤î¿î6î´î"]�î#Z�î%?î(áï@Žî¤î¿î6ï>î¤î¿î6 î û�î!ø�î#Ýrï;—î$îÁîî¸îªîM î%zî(dî*ƒî,&î0qî3@î5< î:éî=+î>½ï9ðîâî¶î’îîâîCî& î(œî*‚î,ãqï7uî¤î~î6 îŠîN î'áî)ýî3*î69î8ñî<°î>uï5ÍîâîõîÏî}î"î$î({î,î.î1áî;Cî?¾ï4&îâî—îî!î&î‘î"¸ î*î+¯î.î4!�î5ûî8’ï1«î¤îîe îPî¬ î%Öî'Šî0Nî2õî5Eî8œî9÷ï0îâîîiî«î!¬î$;î'„î+áî/6î7öî:°î?¾ï.\îâîLîC�î«î„î#î&ìî)áî3aî6*î;Gî=åï,µîâî'îî ®î*óî-jî0Êî2î6 î=µî?¾ï+îâîå�î±î8îœî Mî$òî'±î*§î-œî/~î7“î9ã ï)fîâî— îîúî2î"î(/î*]î,®î/xî3¹î5dî70î:ìï&ëî¤îwî€îãîî±î$‡î)j�î*˜î/ î5Eî7fî< î?sï%Dîâî1îîTî8îûî×î"î&eî'óî)à î2 î8úî;‘ ï#œîâî8îæîF î¥îZî!î#rî'=î-žî0l î7î9zpï NîâîˆîÆîî@qïÿî¤î£î‡îØî$Oî&Šî*¬î-øî2©î5ïî7›î::ïWîâîîÑ{ïîâîîøî& îºqï>î¤î±î² î î%Óî'sî)Wî.Œî4;î8žî:Œ�î;ëî@pï—îâîÏî7î¶î Iî&î+@î.rî4î7åî=ïðîâî2îîwî|î"Jî%Nî'?î+òïtî¤înî¢îëî!=î#¤î%Oî'¡î.Xî1î7î9›î<Èî?rï Íîâ îpîFï Í�ï ÍîÊqï Íî±pîŽï Í�ï Íî ?qï Íî#®î'÷î+7î.Žî23î4�î5Vî:Iî=�î>jrïî Ùî#î*$î.Ÿî1G�������á��������TVm$ï������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS11quad,ifsharedisfalsethennoothercachecontainsacopyofthequad.However,ifsharedistrueothercachesmayormaynotcontainthequad(thereisuncertaintybecausewhensharingstopsthisfactisnotdiscoveredimmediately).Owneristrueifandonlyifthelastwriteintothequadwasintothisverycache.AcacheinitiatesaReadQuadwhenitgetsamiss;itissuesaWriteQuadwhenaquadneedstoberemovedfromthecachetomakeroomforanotherquad(onlyquadswithownersetneedtobewrittenbacktomemory);anditissuesaWriteSingleandsetsownerwhenitsprocessordoesawritetoaquadthathassharedset.WhenacacheissuesaReadQuad,WriteQuad,orWriteSingleallothercachesonthebusmatchthequadaddresstodetermineiftheyholdacopyofthequad.AnycachethatmatchesassertsMnSharedtosignalthatthequadisshared.DuringReadQuadsthemasterandallmatchingslavescopythevalueofMnSharedintothesharedbitforthatquad.Also,whenacacheissuesaWriteSinglethemastercopiesthevalueofMnSharedintothesharedbit.Thisensuresthatsharingisdetectedassoonasitstartsandiseventuallydetectedwhenitstops.DuringReadQuad,WriteQuad,orWriteSingle,allmatchingquadsexcepttheonesupplyingdatatothebusloadnewvaluesfromthebusandcleartheirownerbits.Theownerbitisseteachtimeaprocessorwritesoneofthewordsofthequad.Ifthequadisshared,theresultingWriteSinglewillupdateallothercopiesofthequadandcausetheirownerbitstobecleared.Thusatanytimeatmostoneofthecacheswillhaveownerset.Ownermaynotbesetatall,ofcourse,ifthequadhasnotbeenwrittenintosinceitwasreadfrommemory.DuringaReadQuad,iftheownerbitissetonamatchingquad,thatcacheassertsMnAbortandsuppliesthedatatotheMbusitself(sincethememorydoesn'tknowthecurrentvalue).OtherwiseMnAbortisnotsetandthememorysuppliesthedata.3.4HousekeepingoperationsWeareleftwithtwoproblemsthatDragonsandprobablyCmachineswillhavetodealwith,andthatthatthebasicMbusoperationsabovehavedealtwithincompletely.Thefirstiscontextswitchesbetweenaddressspaces.Whenaprocessormovesfromoneaddressspacetoanother,alloftheoldvirtual-to-physicalassociationsinitscachesthatarenotalsopresentinthenewaddressspacemustbebroken.TherearetwowaystosolvethisproblemwiththebasicMbusoperations.First,theprocessorcanissueasequenceofPbusreferencesthatvictimizesalldatainallitscaches.Second,asequenceofMbusDonecommandscanbegenerated,incooperationwithasophisticatedslave,toclearVPValidinallcachesforallphysicalpagesthatmightbeknowntotheprocessor.Bothofthesesolutionsaresoexpensiveastoprohibitfrequentcontextswitchesbetweenaddressspaces.Thesecondremainingproblemismultiportmemories.Somememorieshavetwoports,aprimaryonewhichattachestotheMbusandasecondaryonewhichdoesnot.SuchamemorymightappearinadisplaycontrollerthatcandoautonomousBitBlt,forinstance.Whenbothportsareactive,ourprotocolformaintainingconsistencydoesnotwork,becausethesecondaryportcandoreadsandwriteswithoutinformingtheMbus.Apartialsolutiontothesecondproblemistotime-multiplextwo-portmemoriesamongseveralaccess-limitedstates.AtanymomentsuchamemoryisinoneofFORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîEqï_/îâî·îîzîäîî 7î";î%Ùî)£î/�î0-î3}î54î7’î;éï]ˆîâî<îšîÿîÜîtî ½î#ºî%wî(tî*âî/ºî2î5Šî9†î:ê ï[àîâîî¼î‘î î"³î%aî&Îî)E î0î9Fî=Íî?:ïZ9îâîCîúîîuîÔîTîÒî"ªî% î(ˆî+4î.î0î3¼ïW¾î¤�î2î�î$�îPî$8î'ïî)Gî,�î-Cî0Øî20î6�î7?î>iïVîâ�îî™îî6î.î åî$Sî&ºî*î,Cî/þî3®î5óî;î>‹ïToîâîÆîÂîÐîÎîî ›î"lî'�î*(î+·î1øî4î5Çî9‰�î:“ ïRÈîâîî!îBîëî¹î#Àî&ã�î(î+rî-�î.1î1£î4eî6Íî;&î>ïQ îâ�îîåîÌ�îüî A î'Çî)‘ î1"î3î6¾î;î=!î?‡ïOyîâîî~îîþî¹î&Gî'³î*Ïî.�î/Bî2 î4eî6Ðî;Bî>RïMÒîâî›îÓîî!»î#Tî')î)âî,,î/”î0êî6�î:´ïL*îâîGî¼îyînî qî$aî'¸î*î-Ìî/Šî6Tî91î;–î@ïJƒîâî îïîJîÒî‡�î ²î$~î(_�î)Š î1î3uî7åî<î>tïHÜîâî•îTî'î€î àî#Îî&âî+Æî.Žî3\î4Âî:7î;ßî?î@ÈïG4îâîvî-î™ î1î"¬î&aî'·ïD¹î¤î€îÑ î%dî';î/1î14î7Eî;[î?¾ïCîâî˜îíîüî´îî!¾î$×î'Ïî,î/xî1âî4‚î7Dî:Ÿî=ðïAkîâï>ïî¤îsî™îîî%î!Nî$k�î%Œî+—î/‘î24î3äî6<î:@î;ñî>Hï=Hîâîwîêî|îûîÌî?î$ø î,–î/Tî3ûî5þî9°î=òî?¾ï;¡îâîXîîµîóî î"²î$Xî&Aî+Êî/@î0Ðî3hî6†î8î;jî>î?¾ï9ùîâî0îØîîGî ;î$¾î'Àî*2î, î.:î/Ðî2î3Ìî8rî9Ðî<-î?©ï8RîâîWî´îgî?î²î!î#³î&Îî*5ï5×î¤î“�îãîGî Îî#Tî'§î)ëî+}î-Àî/ì�î1<î7`î;]î>Rï40îâî î.îÔî!î#_î&Sî'ñî*?�î, î.Žî1Úî5µî8î=`ï2ˆîâî³î$îÿî!î%µî+åî-bî/éî2î4àî7Qî<Ðï0áîâîA{ï-’îâîîþ qï*Cî¤îîZî¼îÃî[î$Pî' î,zî/î4Ü�î6Jî<@î>×ï(œîâîÛîîÜîÝîöî!î#¸î'v�î)šî,{ î3sî7Àî;Qî?ï&ôîâîšîMîîHî"øî(7î-î2Fî7î;�î< ï%Mîâîýî;î¾î€î!î"’î'Íî)”î+%î-\î/î:µï#¦îâîµîµî*îî—î1î"#î'î(ïî+tî.‡î3–î7qî:þî=ï!þîâîõîZîî†îFî Ôî#‡î)î,Iî.ºî2?�î4+î6Ó î>ï WîâîAîSîÝî9�îaî$Iî&�î'Vî)ë î0lî39 î9Žî;}î>î@.ï°îâîçîgî¾�îî#%î%�î'î)Íî-Âî4Òî7‡î9¢ î@pïîâ î[îo�î‘î"±î&iî(î+[î0Øî2î4hî8±î:çî<Ðïaîâî’îFî#îùîdî øî#= î)÷î-9î.×î2Fî7ñî:*î;Óïºîâîî>îŒîî!ñî'Uî,Ãî1ï>î¤î”î>îØî%uî&ùî-1î4‡î8uî>×ï—îâîî‚�î»îî¼î"Ùî( î)Ýî,L�î.5î0Ûî3¡�î4Úî;Uî>ïðîâînîwîG�îÍî!–î%éî*Ìî,Ö�î.\î3j î:î=0î@ïHîâ îñî‚îî$¯î) î,‡î0Gî2Ýî7cî:0î?áï¡îâ îf î‡î ¥î#î&Ìî+Üî.)î4ƒî7kî9åî;Úî?gïúîâîäîðî[î º�î"”ïî¤�îîOîyîî Vî$Ðî*<î+î-% î6Rî;Ôï ×îâî„î1 î!î%Íî'åî*¢î0,î3z�î4Àî:Jî;Òî=î@erïî Ùî#î*$î.Ÿî1Gÿ�������R��������TVm$g����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS12threestates:eitheritssecondaryportisentirelyinactive,orelsetheMbushasnoknowledgeofit,orelsebothMbusandsecondaryportarepreventedfromwriting.Thissolutionisabittoocoarse.Wecanrefineitbyallowingeachpageinsuchamemorytobeinoneofthethreestatesindependentofthestatesofotherpages.TodealwiththefirstproblemweintroduceanoperationcalledDeMapping(breakingvirtual-to-realassociation,leavingorphansinthecache).TodealwiththesecondweintroduceLaundering(rewritingalldirtyquadstomemoryandleavingthemclean)andFlushing(clearingRPValid).(FlushingappearsnottobenecessaryifReadQuadsalwaysrefillcleanorphansfrommemory.LaunderingandDeMappingsufficeinthatcase.)Collectivelywerefertotheseashousekeepingoperations.Forefficiencyhousekeepingoperationsapplynottosinglephysicalpagesbutrathertosetsofphysicalpagesmatchingamaskof{0,1,don'tcare}"trits".Housekeepingoperationscanbeappliedtoallcachesatthesametime,ortoasinglecache.Eachcachecontainsapairof32-bitregistersthattogetherholdthephysicalpagemasktobeused.Inaddition,eachcachehasasinglehousekeepinginitiationregisterlocatedattwoI/Oaddresses:abroadcastaddress,andaprivateone.1bitsstoredintoappropriatebitsoftheinitiationregistercauseinitiationofDeMap,Launder,andFlush.(IfwecoulduseaddressesinESScachemailboxspace,therewouldbeawayofnotifyingprocessorsattachedtoESScachesthatthesehousekeepingoperationswerebeinginitiated.)ThisallimpliesthatacacheneedstorespondasaslavetoitsownIOWrites,andprobablytoitsownIOReadsaswell.Itisnotnecessaryforcachestorespondtoflow-controlledIO.LaundercanrequireenoughMbuscyclestotransportalldirtyquadsineverycachebacktomemory.WhileaLaundryoperationisunderwayeachcachere-arbitratesfortheMbusforeverydirtyquadthatitownsandneedstostore.RequestsfromthePbussidedemandingMbusservicehavehigherprioritythantheoperationrequests.Thesestipulationstogetherpreventahiccupfromoccuringinthesystemwhenthereisagreatdealofdirtydatatobelaundered.NotonlyLaundry,butallhousekeepingoperations,dependingontheirimplementations,maytakemanycyclestocomplete.Conceptuallyeachcachemaintainsahousekeepinginprogressbitthatindicatesthatahousekeepingoperationhasbeenstartedinthatcachebutnotyetfinished.WhetheranoperationisinprogressinanycacheinthesystemcanbeknownbyobservingthestateoftheMnHousekeepingInProgresswirefortwosuccessivecycles.Ifitisnotassertedinsomecyclei,thenanycachewithanoperationstillinprogresswillassertMnHousekeepingInProgressincyclei+1.Ifitisassertedincyclei,theneverycachewillde-assertitincyclei+1.MnHousekeepingInProgresswillthustoggleonandoffuntileverycachehasfinishedthelasthousekeepingoperation.EachcachehasameansbywhichMHousekeepingInProgress[i+1]ORMHousekeepingInProgress[i]maybereadfromitsPBuswithoutneedingMbuscycles.Thealertreaderhasalreadynoticedthatconcurrenthousekeepingoperationscouldbeanightmare.Weavoidconcurrencybymaintaining,asasoftwareconvention,aglobalhousekeepinglockinshared(andalwaysmapped)memory.Todohousekeepingaprocessmustacquirethelock,verifythatprevioushousekeepingisfinished,initiatetheoperation,and(iflogicallynecessary)holdthelockuntilhousekeepingisonceagainfinished.FORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîEqï_/îâîwî²î«î’î# î&î'ˆî,”î2î3Þî6¡î9 �î:ôî=–î@ï]ˆîâî½îmîîÌîyî ¬�î"|î% î'·î.î1 î3Sî9·î=ï[àîâîîHî¸�îçî îxî#‹î&î(«î,¦î.î0î5Šî8¿î<î=¾î@ô�ïZ9îâîOîþîîîœîHîî aî#êî'Ÿ î/Žî1Gî3§î7\î9î<´ïW½î¤îìîîDîÅî¿î%eî'®î-ûî0 î6Xî:rïVîâîþî›î$Ëî){î.°î0Qî2£î7ªî9Äî<±î?¾ïTnîâî†î¿îû î#w î)Þî+àî/Dî3Xî5î:˜î=aïRÇîâî¸îîî î&rî,¾ïRÇ�ïRÇî-î1óî69î8nî:î;Ïî@éïQîâîÎîPîôîÎî"î$·î)º î/¥î1Ïî7ðî;rî<Èî?qïOxîâîîÍîÀî î$<î&Œî/Í î8›î;é ïMÑîâî´ î•î"“î%;î'î+;î0¼î4ºî7nî;¯î=‘î@eïL)îâîî¬îƒ�î†î!òî#ƒî%™î&ÿî*lî-äî2 î;p ïJ‚îâîmî^îHî÷îçî 7î!Ïî$/î'¬î+*î,îî.œ�î/Æî3±ïHî¤î;î+î³�î î"ýî$Úî(öî.}î1pî6øî:Mî<ÐïF_îâî*î¾înî`î{îKî%î(Fî,î.Š�î/µî3¡î<A ïD·îâî¹îpîî¥îj î%ð�î'î-5î2pî5�î6Bî:×î>O�î?|ïCîâîEî] îüî Þî"×î%v î+’î0°î4¥ î:Âî<ºïAiîâîÀînrîïAi�ïAiîxî¥îWî"Xî$Hî)î*mî,Çî/Èî3þî74î:�î=Qî>×�î?½ï?Áîâî(î½ îéî1înî!µî%î'2qî)ëï?Á�ï?Áî*² rï?Áî2U î7’î:î= qï=Eî¤îÎîÎî¦î…�î¾î#šî'Œî)Jî.î0[�î1•î5î6Êî8µî;Éï;žîâîšîlîîöîûî#·î%eî)0î*¨î,î.Šî4žî6Üî;-î<Üï9öîâîî!ï7zî¤î4îÁî‹î#w�î%Rî'êî+ãî-“î3qî5cî8¶î<ºî>jï5Óîâîî²î¿îÄî$;�î%Ãî+¼î2Dî4î:Âî>Rï4+îâî²îî–�î”î Oî"°î&ˆî)ýî- î0’î2î5¸î8“î<˜î>jï2„îâîÓîNîÂ�î,îÖî!Ãî(þ�î*ìî-—î21î5Œî9ïî>øï0ÝîâîFîtî²î!¸î)î.nî3s�î4¡î9î<ƒï/5îâîîðîkî î©î �î!>î$±î'ªî)cî,µî/ºî1hî3Y ï,¹î¤îóîŒîýî!ýî$lî-‰ î5î<Rî>×ï+îâîéî8î ~î$”î(×î*Ñî2,î:Õî>Rï)kîâî�pî)ï)k�ï)kîå îdîùqî%)ï)k�ï)kî%ðî'5î)òî/‘î2N�î3gî;ôï'Ãîâî€îîªîîxî"mî%î'µî*&î0–î6pî8‰î>Ûî@pï&îâîvîKîîîÚî!`î&î(´î*Ìî/xî1›î8î:‡î=ßî?¾ï$uîâî Lî#qî%Æî(‰ î/î4 î5¦î7î8–î;"î@pï"ÍîâîëîÔî‰î%î<î#~î'î)tî0î3*î5Nî;2î>Sï!&îâî aî";î%Úî*î+µî-7î.Ïî42î6î9¬î;î>jïîâî¦îJîôîBîéî!Uî%î6eî9 î<î@ï×îâî›îÎîîÌî™î!î&Sî(´î+5î3Õ î:Þî>Rï0îâîå�îîoî"øî)”rî?éï0�ï0î@Æ�qï‰îâî Êî$î&$î)qî- î/î2Óî8î={�î?‡ïáîâïeî¤îšîÝî@îÓî#Åî(Âî+¯ î2³î;p ï¾îâîîe�îò î!î"î&1 î.Wî0¶î9î;�î<¥ïîâ î7�îMî[î#æî&Ëî(eî,¶î/Óî4#î9Öî?÷ïoîâîâîz�îžîkî"Íî'¦î)ÿî-Jî1/î3öî9ïÈîâî€îMîî® î$bî'Lî)Xî.ø î5·î9î;¬î>×ï îâîîìî3îÜrïî Ùî#î*$î.Ÿî1G���������������TVm$J��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS134.BusTimingThissectiongivesthedetailedtimingofbusarbitrationandofeachofthetransactionsjustdescribed.Inthetimingdiagrams,eachrowcorrespondstoonebuscyclefornon-idlecycles.Idlecyclesarerepresentedbyarowlabelled"wcycles",wherewindicatesthenumberofidlecycles.ActionsduringeachcycleareindicatedusingMesalikestatements.NotethatthebooleanvalueTRUEcorrespondstothehighvoltagelevelandthebooleanvalueFALSEcorrespondstothelowvoltagelevel.Forexampleanegativelogicsignalxwouldbeassertedasfollows:x_FALSE.ThediagramsdonotdescribethetimingofMParity,sincethisisalwaysonecycledelayedfromthevalueonMTransport.Ineachdescription,therequestorassertsMnRqincycle0andthearbiterassertsMnGntincycle1.Anarbitrarynumberofcyclesmayoccurbetweencycleslabelled0and1.4.1ArbitrationThetimingforarbitrationappearsinFigure2.ArequestorassertsMnRqduringphaseAofcycle0.ThearbiterlatchestherequestduringtheBofcycle0,andifthebusisfreeMnGntgetsassertedintheAofcycle1.Thenewmastercandrivethebusatthebeginningofcycle2A.Thustheminimumarbitrationdelayistwocycles.Ifthebusisnotfree,zeroormorewaitcyclesareinsertedimmediatelyaftercycle0.TheearliestMnRqcanbedeassertedisduringcycle2+w.TheearliestMnGntisdeassertedinresponseisduringcycle3+w,andtheearliestanewdevicecanbecomemasterisduringcycle4+w.TheearliestMnNewRqmaybeassertediscycle3+w.Itmustbedeassertedinthefollowingcycle.4.2ReadQuadFigure3showsthetimingforReadQuad.Cycles0through1aretakenupbyarbitration(recallthatweareassumingtheminimumarbitrationdelay).Thetransactionbeginsincycle2.ThemastersetsMCmdtoReadQuad,MAddrtoRQAddress,andassertsMnAdCycle.Cycles3and4donottransmitanydata.Duringcycle3themasterdeassertsMnAdCycleandduringcycle4anymatchingcacheassertsMnShared,andifitsownerbitisset,assertsMnAbort.InthefollowingcyclememorydeassertsMnSharedandthecache,ifany,thatassertedMnAbortdeassertsit.Aftercycle4theslavemayinsertanarbitrarynumberofwaitcycles,w>0.Incycle5+wtheslave(respondingcacheormemory)assertsMnDVtosignalthatdataisvalidandsendsthefirstwordofthequadonMData.Duringcycle6+wtheslavedeassertsMnDVanddrivestheseconddatawordontoMData.Duringcycle7+wtheslavedrivesthethirddatawordontoMDataandthemasterdeassertsMnRq.During8+wtheslavedrivesthefourthdatawordontoMDataandthearbiterdeassertsMnGnt.NotethattheminimumnumberofcyclesforReadQuadis7,assumingzeromemorywait.FORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîEzï^õîâî¾î qï[¦î¤îðîÀîdîöî%aî)íî+Ùî.¢ î5™î8ƒî:oî=Óî?¾ïYÿîâî€î@ î ‚î"pî$íî)fî/¸î3î5ç î=¦î?rïXWîâî î;î î@î"bî&î*-î,¨ î4:î6]�î7¯î:˜î?ëïV°îâîÝîð�îmîî!tî&›î(Oî+î/Êî4Åî90î<\î?ÊïU îâî¾îOîàît î%Ùî)7î+îî.5î3Srî6åïU �ïU î7žqïU î:} ïSaîâî|îÇîØî€î²î Tî"Ÿî'Árî+VïSa�ïSaî,qïSaî/d î6ðî8Šî:Õî=aïQºîâîbî=îå�î>î"Ûî&[pî*vïQº�qïQºî+ðî0Nî2nî7Ôî9±pî?ïQº�qïQºî@‘�rïPîâqî€ïP�ïPîîîî1î!Äî'Eî)Ãî.;î0î5ßî9pî<0î=¹ïNkîâîŽîîî~îÝî#‡î% ïKðî¤îYîpîÁî î&�î*6î.î0!î3z�î4•î72î9xî=ÏïJIîâîÍîgîÅî¬îëî"{î'“î)7î-î0 î3µî9î<òïH¡îâ�îîÎ{ïCªîâî qïA/î¤îµîHî¾ î"¼î(�î)çî.î1�î2Øî9%î=ï?‡îâîUî9�îÈîƒîøî î"èî'[î+åî.Fî3î7î9ò�î;`î=î@‘ï=àîâî‘îèî?îÍî0îôî ëî#¯î(Þî*ƒî,Ú�î.]î0î3xî5wî8Fî;+î?“ï<9îâîuîÞîî!î‹î"�î#Ãî'@î)ßî-gî/Ðî60 î<þî@²ï:‘îâî‡îLîÇî î°îî ƒî#¡î&î(Zî+æî.Ùî2Éî5î:F ï8êîâîî‘ï6oî¤îjî îiîâî!Á î(Sî)î.î1lî5·î8~î=ï4Çîâîq î8î îÒî aî$õî(‹î,™î/tî1÷î6Ì�î8î;+î?“ï3 îâîî¨î4îÄî"Wî'î)þî.Ðî6'î9Jî;[î@²ï1yîâîUîÄî;î£î” î$8î%æî(Eî.X{ï,‚îâîqï*îî†�î±îµîî"]î$‘î,@î0’�î1½î6ì�î8î:bî>î@"ï(_îâ î¦îÔî£îÊî!î'î)zî/Ð î6”ï%ãî¤î` î?îrî!î$[î&3î(ïî-Dî/Éî4uî6î=)ï$<îâîŸ îpî6î” î(Oî,¸�î-üî0Â�î2î4î6Ÿî<î>Áï"•îâîÂîK�î—î î”î%fî->î0î4“î8�î9hî< ï íîâî’îÅîÆî aî!¦î#dî'vî)wî*Çî- î1Sî8î9Èî<ïFîâî‡î&îî% î'òî*„î.Ùî0lî3—î6—î;ÿïŸîâî©îóîî�î\î!Çî%:î(Iî, î.î3Íî9î:Éî=Îpï÷îâ�|îÉï÷�qï÷î#ï|î¤îvîíî„îçî R î'ëî+»î-‚î3lî7¿î<€î>3ïÕîâîÐîôîîîÝî ¼î#;î&2î)Úî+³î.1î1Ïî3õî9Ãî>«ï-îâî³îQîöîðî#ìî&âî+-î-Ëî2›î5Þî9¥î=ï†îâî¨îî©îî jî$tî&Ñî*6î-9î0¾î3ìî8œî;Qî=®ïßîâî±î$î�î"¦î%î(“î,³î/&î3sî6‹î:'î=kï7îâî™îùîiî%ï¼î¤î;î*îªî! î&mî(Fî,^î.¼î5Ãî7Oî8ýî?ï îâîOïmrïî Ùî#î*$î.Ÿî1Gÿ������� ��������TVm$vCOMMONMBUSSPECIFICATIONS144.3WriteQuadFigure4showsthetimingforWriteQuad.Cycles0through1aredevotedtoarbitrationasusual.Duringcycle2themastersetsMCmdtoWriteQuad,MAddrtotheaddressandassertsMnAdCycle.Duringcycle3themasterdrivesthefirstdatawordontoMDataanddeassertsMnAdCycle.Duringcycle4themasterdrivestheseconddatawordontoMDataandiftherearezerowaitstates(w=0)thememoryassertsMnDV.Duringcycle5themastersendsthethirddatawordonMDataandiftherearezerowaitstates,deassertsMnRq.ThememorydeassertsMnDViftherearezerowaitstates,orassertsMnDVifthereisonewaitstate.Incycle6themasterdrivesthefourthwordontoMData,anddeassertsMnRqifthereisonewaitstate.IftherearezerowaitstatesthearbiterdeassertsMnGnt.ThememorydeassertsMnDVifthereisonewaitstate,orassertsMnDViftherearetwowaitstates.Incycle7,iftherearetwowaitstates,themasterdeassertsMnRqandthememorydeassertsMnDV.IfthereisonewaitstatethearbiterdeassertsMnGnt.IftherearethreewaitstatesthememoryassertsMnDV.Finally,thereareanarbitrarynumberofwaitcycleswhichareterminatedbythememoryassertingMnDV,followedinthenextcyclebythemasterdeassertingMnRq,andinthenextcyclethearbiterdeassertingMnGnt.NotethattheminumumnumberofcyclesforWriteQuadis5.4.4WriteSingleFigure5showsthetimingforWriteSingle.Cycles0through1aredevotedtoarbitration.Duringcycle2themasterdeassertsMnRq,setsMCmdtoWriteSingle,setsMnAdrtotheaddress,andassertsMnAdCycle.Duringcycle3themastersetsMDatatothedataanddeassertsMnAdCycle.ThearbiterdeassertsMnGnt.Duringcycle4anymatchingslaveassertsMnShared.Duringcycle5anymatchingslavesdeassertMnShared.4.5IOReadFigure6showsthetimingforIORead.Arbitrationtakesplaceduringcycles0through1.Duringcycle2themasterassertsMnAdCycle,assertsIOReadonMCmd,assertstheIOregisteraddressonMAddr,anddeassertsMnRq.Duringcycle3,themasterdeassertsMnAdCycle,andthesingleslaveassertsdataonMData.4.6IOWriteFigure7showsthetimingforIOWrite.Cycles0through1areforarbitrationasusual.Duringcycle2themasterassertsMnAdCycle,assertsIOWriteonMCmd,assertstheIOregisteraddressonMAddr,anddeassertsMnRq.Duringcycle3,themasterassertsthewritedataontoMDataanddeassertsMnAdCycle.4.7IOReadFlowFORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE{ï_,îâîqï\±î¤î�î^îvîàî"Eî$Ž î,§î1�î2Lî7�î8Îî;-î@oï[ îâ î¦îUïXŽî¤î‘î(�î‚îî"šî%`î*Mî, î3Äî8Ýî:°î=4ïVçîâîŸîõ îžî#mî&æ�î(!î*‡î.ýî3î5vî8Tî;_î>íïU@îâî…î-îÙ î$Wî)î,t�î-™î/éî4Jî8Gî:—î?ïS˜îâîPîeîýîšîàî!Nî#‡î&pî)Nî,é�pî-bïS˜�qïS˜î.Iî1=î3‚î8Ôî= ïQñîâîžî�î,îîãî"–î$éî(Dî+=î.¹î0²î5Xî8î9Wî<Ôî?ïPJîâîóîîìî!gî$Wî)Üî/¯î4…î5ýî9žî< î?%ïN¢îâîùîÇîîçîQî"äî$Yî'î*î.1î0 î3‡�î4Åî7.î;¨î?¾ïLûîâî2îÐîî7î"î'Öî,\î-Óî1rî2ôî5µî8Äî<ýî>•ïKTîâîCîTî[îî‹î" î'Òî-Éî0®î6)î;òî@½ïI¬îâîtîéîžî î3î�î#Xî(î)‰î-î/xî2-î5/î9Óî;«î?'î@½ïHîâîŸî'îî4îvî" î&®î,î1Bî4-î6Áî<bïF^îâîœî.îÈîDî�î! î$Kî&»î+<î1î7î8—î<1î>•ïD¶îâîøîÊîGîÑî"=î(î-6î0Üî3Lî5Zî;î@eïCîâîìîóîîu î#vî%‚î'òî-pî3%î8Kî>�î?¾ïAhîâî@îîLîúî¸ î'î,/î/5î12î3àî7>î:ÿî=ï?Àîâ îóï=Eî¤îîèîHî!î&-î'æî+Þî.î5Cî6®{ï8Nîâî qï5Óî¤î�îPîaîÄî""î$cî,Ñî1/�î2hî7¤�î8Üî;4î@oï4,îâî|îBî²�îäî"@î&®î,fî1,î3Êî8î:;ï2„îâî€îqîîxî·î"kî&· î/Mî4î7‚�î8´î;î?}ï0Ýîâî|îîXîDîãî"† î*ñî-°î2î7«î=Uï/6îâîb�î£îPî[îÏî$*î+äî0ºî49�î5zî8(î>3ï-Žîâî{ï(˜îâîqï&î¤î�îEîPî®î"î$Bî*Q î1vî4òî8…î<ôî@é�ï$uîâîï!úî¤îQî©�îÃîî!\î% î-Žî1Âî6Þî8Éî=Ïï Sîâî5îDîîóîìî$,î&×î,†î1¸î6uî9Ûî;[î=®ï«îâîž î·îoî!Îî%¹î) î-oî0tî2{{ïµîâîqï:î¤î�îOî_îÁî"î$_î*ºî/�î0Oî5Š�î6Âî9î;Y ï’îâîïî¤îKî�î±îïî!>î%l î-eî1“î6êî8Ïî=Ïïpîâî5îDîîóîìî$,î&×î,†î1¸î6uî9Ûî;[î=®ïÈîâî1î‘îîîCî#öî&®î,i {ï Òîâî rïî Ùî#î*$î.Ÿî1G�������4��������TVm$Ù������������������������COMMONMBUSSPECIFICATIONS15Figure8showsthetimingforIOReadFlow.Cycles0through1areforarbitrationasusual.Duringcycle2themasterassertsMnAdCycle,assertsIOReadFlowonMCmd,assertstheIOregisteraddressonMAddr.Duringcycle3themasterdeassertsMnAdCycle.Followingcycle3therecanbew>0waitcycles,duringwhichtheslavedoesnotassertMnAdCycleandMCmd=Doneduringthesamecycle.Duringcycle4+wtheslaveassertsMnAdCycle,setsMCmdtoDone,andsetstheordersfieldofMDatatoNoClear(othervaluesareacceptableiftheslaveisthemap).Incycle5+wthemaster(slave?)deassertsMnAdCycle.TheslaveassertsthedataonMDataandthemasterdeassertsMnRq.4.8IOWriteFlowFigure9showsthetimingforIOWriteFlow.Cycles0through1areforarbitrationasusual.Duringcycle2themasterassertsMnAdCycle,assertsIOWriteFlowonMCmd,assertstheIOregisteraddressonMAddr.Duringcycle3,themasterassertsthewritedataontoMDataanddeassertsMnAdCycle.Followingcycle3therecanbew>0waitcycles,duringwhichtheslavedoesnotassertMnAdCycleandMCmd=Doneduringthesamecycle.Duringcycle4+wtheslaveassertsMnAdCycle,setsMCmdtoDone,andsetstheordersfieldofMDatatoNoClear(othervaluesareacceptableiftheslaveisthemap).Incycle5+wthemaster(slave?)deassertsMnAdCycle,reassertsthewritedata,anddeassertsMnRq.4.9MapRefandMapRefDirtyFigure10showsthetimingforthesetwotransactions.Cycles0through1areforarbitrationasusual.Duringcycle2themasterassertsMnAdCycle,assertsMapRef(orMapRefDirty)onMCmd,assertsthevponMAddr[7..32).Duringcycle3,themasterdeassertsMnAdCycle.Followingcycle3therecanbew>0waitcycles,duringwhichtheslavedoesnotassertMnAdCycleandMCmd=Doneduringthesamecycle.Duringcycle4+wtheslaveassertsMnAdCycle,setsMCmdtoDone,andputsrp,orders,andflagsontoMData.Incycle5+wthemaster(slave?)deassertsMnAdCycle.FORINTERNALXEROXUSEONLY���qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîEqï_/î¤îf�îíîLîþî#«î&: î/öî4¢�î6)î;´�î=;î?áï]ˆîâ î¦îUï[î¤îpîæ�îîî!ôî&G î.dî2¶ î:ôî<ýïY_îâîiî�îTîkî"Œî$Ëî+î0î3¶�î5#î7ºî<bïW¸îâ îÄîgî!ü�î#Sî&þî)¬î+¿�|î,½ïW¸�qïW¸î.�î/nî2‰î6ûî;Žî?¾ïVîâî6îSî´îlî#î%½î/î3wî5Ãî9-î=UïTiîâîfî îzîòî R î(|î+.î0î1Çî5ûî8Ãî;uî=åïRÂîâîîÈîyî&î¶î#Íî'ùî*K î0ùî2Xî4¶î8î9…î;ãî@OïQîâîXîïîRîÅî!±î'p î0î2ðî6Zî:î=î@ïOsîâî•îLî¬îî"Ø{ïJrîâî qïGñî¤îa�îãî=îêî#‘î&î0î4¶�î68î;¾�î=@î?áïFJîâ î¦îUïCÉî¤îiîÙ�î îfî!Óî& î.6î2 î:úî<ýïB"îâîMîÉîîüî"î$%î*-î/î2¢î4Kî6Æî;Sî?¾ï@zîâîkî|î¸îwî :î& î.¶î5Bî8Á�î:î=–î@-ï>Óîâ�|îàï>Ó�qï>Óî:�îÿî‰îjî kî% î'úî+òî/³î2¹î7î?gï=,îâîÍî¹î ”î$Œî)Ñî/î3î7î9ìî=Ïï;„îâ îîÈî¦î jî$£î'pî*'î,œî0êî40î5ÿî:Èî<Œï9Ýîâî,îŒî î óî"…î%î(°î*Mî,Þî1²î3³î7Wî;î=®ï86îâîËî‡ î! î'î)xî,öî0Sî3î8Æ{ï34îâîîvî qï0³î¤îîîîxî"Öî%î(¦î+Wî3¼î8�î9Tî>‘�î?Êï/îâî îäî’ï,‹î¤îMî¡�î·î÷î!Hî%x î-sî1£î6òî9ï*äîâîîIî¹î9îTî!{î+(î0î3¥î5Rî7Òî<bï)<îâ îÄîgî!ü�î#Sî&þî)¬î+¿�|î,½ï)<�qï)<î.�î/nî2‰î6ûî;Žî?¾ï'•îâî6îSî´îlî#î%½î/î3wî5Ãî9-î=Uï%îîâî\îõî[îÉî î(?î*çî/¶î1kî5•î8Rî;^î=ï$Fîâî™îÔîî“îcî"Öî&iî(Èî-8î2!î7Ý rïî Ùî#î*$î.Ÿî1G�������¡��������TVm$������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS16BusCouplerROMBootOthersInterfaceEthernetDiskInterfaceI/OprocessorVME BusCacheMap Processorwith Map CacheModuleMemoryDragon ModuleDragon ModuleIFUEUFlt. Mult.Flt. AddInstr.CacheDataCacheDragon ProcessorDragon ModuleMemoryModuleMemoryModuleControllerDisplayM BusFigure 1. A Dragon ClusterFORINTERNALXEROXUSEONLY���qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE}øÿúÿî#ï`þä�$î#ï[Âþ�$rî#ï[žþ �$î#ï[Âþ�$rî\ï^fî\ï\»î±ïIúþ�ksî#ïYeþä�$î#ïUþ�$rî#ïUþ�$rî#ïTóþ �$îêïVîêïW»î#ïR»þä�$î#ïNlþ�$rî#ïNlþ�$rî#ïNIþ �$î\ïP‚î ïQžî ïSIî[ïP‚þ �$î?ïP¥þ�$rî[ïP¥þ�$rî[ïTóþä�$î[ïW,þ �$î?ïWPþ�$rî[ïWPþ�$rî[ï[žþä�$î ïYôî ïXIî[ï]×þ �$î?ï]ûþ�$rî[ï]ûþ�$rî[ïbIþä�$î ï`Ÿî ï^ôî[ïJeî?ï`þr�$î?ïYeþr�$î?ïR»þr�$î±ï]×þr�$î±ïW,þr�$î±ïP‚þr�$î'xïbIþä�$î'xïY‰þ�$äî0\ïY‰þ�$äî'xïYeþ �$î)±ï]×î#ï]×þr�$î'xïTóþr�$î'xïIúþ�$î5ëïIúþ�$î'xïI×þ–�$î)±ïOóî)±ïNI îB$ïW,þ�$îB$ïIúþ�$ VîMAïIúþ�$ VîB$ïI×þ@�$îEyïOeîEyïQî;yïP‚þ«�$î5ëïOeþŽ�$î;yï¿þ�kVî#ï Õî?ïœþ!z�$î?ï¿þ�$rî?ïþ!V�$î?ï¹þ!V�$î?ïjþ�$rî?ïGþ!z�$î#ï€î?ï5úþ�$9î#ïNþ�$(îxïNþ�$(îêï8þÎ�$î”ï83þ�$«îêï83þ�$«îêï>ºþ«�$î#ï;dî”ï;dþ«�$î”ï0Hþ«�$î Íï Üþ�$î#ï2îêï5Öþ«�$îêï/Oþ�$«î”ï/Oþ�$«îêï/+þÎ�$îxï) îêï,òþ«�$îêï&kþ�$«î”ï&kþ�$«îêï&GþÎ�$îêï$þ«�$îêï‡þ�$«î”ï‡þ�$«îêïcþÎ�$îxï ¹îxïC,þ�$î”ï ¹þ]�$îxï+þ²�$î%?ï>ºþ«�$î%?ï83þ�$«î+êï83þ�$«î%?ï8þÎ�$î&êï;óî&êï:Hî%?ï3þ«�$î%?ï-þ�$«î+êï-þ�$«î%?ï,òþÎ�$î&êï0Öî&êï/+î”ï)þ9�$î”ïAî?ïþ�$.¬î[ïEóî?ïGžþ!V�$î?ïòþ!z�$î2•ïþ�$.¬î2•ïjþ�$rî2•ï¿þ�$rî+êï;dþy�$î/@ï0kþ�$î+êï0Hþy�$î/@ï5Öþ9�$î2•ï€þä�$î2•ï Õþä�$î0\ï]×þ�$î;yï<þ«�$îEyï=îEyï;dîB$ï5Öþ@�$îMAï5úþ�$ VîB$ï5úþ�$ VîB$ïC,þ�$î;yï(€þ«�$îEyï)îEyï'dîB$ï!Õþ@�$îMAï!ùþ�$ VîB$ï!ùþ�$ VîB$ï/+þ�$îDëï îDëïÕî=$ïî?ëïcþ�$î?ëï1þ�$ VîOzï1þ�$ Vî?ëïþ²�$î;yï¹þr�$î$#ï*rø�ú�ïî Ùî#î*$î.Ÿî1G�������O��������TVm$=����������������������������������������������������COMMONMBUSSPECIFICATIONS17Figure 2. Timing for Bus Arbitrationarbiter: latch request;4+w3+w2+w(w>=0)w cyclesABABABABAB0PhaseCycleBA<<first transaction cycle>><<earliest next master>>1+wrequestor: MnRq _ FALSEarbiter: MnGnt _ FALSE;<<earliest master: MnRq _ TRUE; or MnNewRq _ FALSE>><<earliest arbiter: MnGnt _ TRUE>>; MnNewRq _ TRUE;FORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE}øÿúÿîï)ð$~îêïLåîÍï3Áþ�$ :î?ï3Áþ�$ :}î [ï7î [ï;óî [ï@e~î?ïHsî°ïJ}îï8�îï6d�î éï5Öþ:å�$îï=�îï:Ö�î éï:Hþ:å�$îïA�îï?H�î éï>ºþ:å�$îïEó�îïCº�î éïC,þ:å�$îïJe�îïH,�î éïGžþ:å�$î éïLþ:å�$î [ïMº�î[ïQžî ”ïS×þ>;�$î ”ïP‚þ>;�$î?ïQžîïLž�îïN×�~îêïAÈîêï8ä}îÍïD×~îêïOîêïF:ø�ú�î(ïAÈð5øÿúÿîêï=Vð3rø�ú�ïî Ùî#î*$î.Ÿî1Gÿ�������f��������TVm$�é������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS18Figure 3. Timing for ReadQuad8+w7+w6+w32w cycles(w>=0)BABABA5+w1ABABABABABAB0PhaseCycleBArequestor: MnRq _ FALSE;arbiter: MnGnt _ FALSE;4slave: {MData _ RQData0; MnDV _ FALSE};AB9+wslave: MParity _ RQData3Parityslave: {MData _ RQData1; MParity _ RQData0Parity; MnDV _ TRUE}slave: {MData _ RQData2; MParity _ RQData1Parity} master: MnRq _ TRUE;w=0 => {some cache: owner => MnAbort _ TRUE; memory: MnShared _ TRUE}master: {MCmd _ ReadQuad; MAddr _ RQAddress; MnAdCycle _ FALSE}master: MnAdCycle _ TRUE;any cache: {match => MnShared _ FALSE; owner => MnAbort _ FALSE}; waitCycle _ 0;memory: MnShared _ TRUE}(waitCycle _ waitCycle+1)=1 => {some cache: owner => MnAbort _ TRUE; slave: {MData _ RQData3; MParity _ RQData2Parity} arbiter: MnGnt _ TRUE;FORINTERNALXEROXUSEONLY���qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE}øÿúÿî!\ï¸î"ï!Õî"ï&Gî"ï*¹î"ï@e�î"ïD×�~î ï7Èî ï6î°ï)þ?W�$}îÍï)�îÍï+Ö�î°ï$þ?W�$îÍï%+�îÍï'd�î°ï +þ?W�$îÍï ¹�îÍï"ò�î”ïþ�$:åîïþ�$:åî"ï0Hî"ïIH�îÍï2�îÍï.�î°ï-€þ?W�$îÍï8�îÍï4º�î°ï4+þ?W�$îÍï=�îÍï:Ö�î°ï:Hþ?W�$îÍïA�îÍï?H�î°ï>ºþ?W�$îÍïEó�îÍïCº�î°ïC,þ?W�$îÍïJe�îÍïH,�î°ïGžþ?W�$î°ïLþ?W�$î"ïMº�î"ïQžî[ïS×þB�$î[ïP‚þB�$î ïQžîÍïLž�îÍïN×�~î±ïOî±ïJ¬}î"ï;ó�~î±ï2Èð'}îÍï€�îÍïG�î°ï¹þ?W�$î"ïc~î±ïÇî±ï,ð>î±ï'«ðGø�ú�îêï1ðEøÿúÿî±ïF:ð?ø�ú�î±ïAÈøÿúÿî±ï=VðPø�ú�îêï7:î±ï8äðEøÿúÿî±ï#9ðHrø�ú�ïî Ùî#î*$î.Ÿî1G���������������TVm$X��������������������������������������������������COMMONMBUSSPECIFICATIONS19Figure 4. Timing for WriteQuadABCyclePhase0BABABABABABA1ABAB23requestor: MnRq _ FALSE;arbiter: MnGnt _ FALSE;master: {MCmd _ WriteQuad; MAddr _ WQAddress; MnAdCycle _ FALSE}4567master: {MData _ WQData0; MnAdCycle _ TRUE}w=0 => memory: MnDV _ TRUE; w=1 => memory: MnDV _ FALSE;master: {MData _ WQData2; MParity _ WQData1Parity; w=0 => MnRq _ TRUE}master: {MData _ WQData3; MParity _ WQData2Parity; w=1 => MnRQ _ TRUE}w=0 => memory: MnDV _ FALSE;master: {MData _ WQData1; MParity _ WQData0Parity} (w>0)w=0 => arbiter: MnGnt _ TRUE; w=1 => memory: MnDV _ TRUE; w=2 => memory: MnDV _ FALSE;w=1 => arbiter: MnGnt _ TRUE; w=2 => memory: MnDV _ TRUE; w=3 => memory: MnDV _ FALSE;waitCycle=w-2 => arbiter: MnGnt _ TRUE; waitCycle=w-4 => memory: MnDV _ FALSE;waitCycle _ waitCycle + 1; waitCycle=w-3 => {master: MnRq _ TRUE; memory: MnDV _ TRUE}w-1 cyclesmaster: {MParity _ WQData3Parity; w=2 => MnRq _ TRUE}; waitCycle _ 1;FORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE}øÿúÿî!\ïœî”ïN×�î”ïLž�îÍïQžî"ïP‚þDæ�$î"ïS×þDæ�$î éïQžî wïMº�î wïLþA�$î wïGžþA�$î”ïH,�î”ïJe�î wïC,þA�$î”ïCº�î”ïEó�î wï>ºþA�$î”ï?H�î”ïA�î wï8þA�$î”ï8�î”ï=�î wï1dþA�$î”ï1ò�î”ï6d�î wï*¹þA�$î”ï+G�î”ï/¹�î wïIH�îÍï‡þ�$6tî[ï‡þ�$6tî”ï"d�î”ïò�î wïcþA�$î”ï)�î”ï$�î wï$þA�$î wïD×�î wï@e�~îxïOîxïJ¬ø�ú�îxïF:ð@}øÿúÿî wï:Ö�î wï4+�î wï.�î wï&Ö�~ø�ú�îxïBð+î±ï5ð8îxï6«ðFîxï0ðFî±ï;¬îxï=Vð3øÿúÿîÍïUø�ú�î±ï.VðVî±ï'«ðVî±ï!�ðNîxï"«ðVî°ï!Ž îxï)VðErïî Ùî#î*$î.Ÿî1G�������Ä��������TVm$7����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS20ABCyclePhase0BABABABA123Figure 5. Timing for WriteSingle4requestor: MnRq _ FALSE;arbiter: MnGnt _ FALSE;master: {MnRq _ TRUE; MCmd _ WriteSingle; MAddr _ WSAddress; MnAdCycle _ FALSE}master: {MData _ WSData; MnAdCycle _ TRUE}; arbiter: MnGnt _ TRUE;master: MParity _ WSDataParity; slave: match => MnShared _ FALSE;AB5slave: match => MnShared _ TRUE;FORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE}øÿúÿî”ïN×�î”ïLž�îÍïQžî"ïP‚þG�$î"ïS×þG�$î éïQžîéïMº�î wïLþCÉ�$î wïGžþCÉ�$î”ïH,�î”ïJe�î wïC,þCÉ�$î”ïCº�î”ïEó�î wï>ºþCÉ�$î”ï?H�î”ïA�î wï:HþCÉ�$î”ï:Ö�î”ï=�îéïIH�îÍï3Áþ�$ :î[ï3Áþ�$ :îéïD×�îéï@e�î”ï$îéï<�~îxïOîxïJ¬îxïF:ðOø�ú�îxïBðBîxï=ðA}øÿúÿî”ï8�î”ï6d�î wï5ÖþCÉ�$îéï8�~ø�ú�îxï8ärïî Ùî#î*$î.Ÿî1Gÿ�������Ž��������TVm$�à��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS21321ABABAB0PhaseCycleBAFigure 6. Timing for IOReadrequestor: MnRq _ FALSE;arbiter: MnGnt _ FALSE;master: {MCmd _ IORead; MAddr _ IOAddress; MnAdCycle _ FALSE; MnRq _ TRUE}master: MnAdCycle _ TRUE; slave: MData _ IOData; arbiter: MnGnt _ TRUE;FORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE}øÿúÿîéï@e�îéïD×�î[ï<¤þ�$VîÍï<¤þ�$VîéïIH�î”ïA�î”ï?H�î wï>ºþA�$î”ïEó�î”ïCº�î wïC,þA�$î”ïJe�î”ïH,�î wïGžþA�$î wïLþA�$îéïMº�î éïQžî"ïS×þDæ�$î"ïP‚þDæ�$îÍïQžî”ïLž�î”ïN×�î#ï&G~îxïOîxïJ¬îxïF:ðJø�ú�îxïAÈðGrïî Ùî#î*$î.Ÿî1G�������"��������TVm$�³��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS22321ABABAB0PhaseCycleBArequestor: MnRq _ FALSE;arbiter: MnGnt _ FALSE;Figure 7. Timing for IOWritemaster: {MCmd _ IOWriteFlow; MAddr _ IOAddress; MnAdCycle _ FALSE; MnRq _ TRUE}master: {MnAdCycle _ TRUE; MData _ IOData}; arbiter: MnGnt _ TRUE;FORINTERNALXEROXUSEONLY���qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE}øÿúÿîéï@e�îéïD×�î[ï<¤þ�$VîÍï<¤þ�$VîéïIH�î”ïA�î”ï?H�î wï>ºþA�$î”ïEó�î”ïCº�î wïC,þA�$î”ïJe�î”ïH,�î wïGžþA�$î wïLþA�$îéïMº�î éïQžî"ïS×þDæ�$î"ïP‚þDæ�$îÍïQžî”ïLž�î”ïN×�~îxïOîxïJ¬}î Íï+Ö~îxïF:ðOø�ú�îxïAÈðBrïî Ùî#î*$î.Ÿî1G�������#��������TVm$�´����������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������COMMONMBUSSPECIFICATIONS236+w32BA5+w1ABABABABABAB0PhaseCycleBA(w>=0)w cycles4+warbiter: MnGnt _ FALSE;requestor: MnRq _ FALSE;arbiter: MnGnt _ TRUE;Figure 8. Timing for IOReadFlowmaster: {MCmd _ IOReadFlow; MAddr _ IOAddress; MnAdCycle _ FALSE}master: MnAdCycle _ TRUE;slave: MnAdCycle _ FALSE => MCmd#Done;slave: {MCmd _ Done; MAddr _ mumble; MnAdCycle _ FALSE}slave: {MnADCycle _ TRUE; MData _ IOData}; master: MnRq _ TRUE;FORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE}øÿúÿîéï.îéï@e�îéïD×�î wï,òþA�$î”ï-€�î”ï/¹�î[ï*Ýþ�$)îÍï*Ýþ�$)îéï3îéïIH�î”ï4+�î”ï1ò�î wï1dþA�$î”ï8�î”ï6d�î wï5ÖþA�$î”ï=�î”ï:Ö�î wï:HþA�$î”ïA�î”ï?H�î wï>ºþA�$î”ïEó�î”ïCº�î wïC,þA�$î”ïJe�î”ïH,�î wïGžþA�$î wïLþA�$îéïMº�î éïQžî"ïS×þDæ�$î"ïP‚þDæ�$îÍïQžî”ïLž�î”ïN×�~îÍï;¬îÍï=V}îéï7~îxïJ¬îxïOø�ú�îxï0}øÿúÿî”ïÕ~îxïF:ðAø�ú�îxïAÈîxï=Vð&îxï9+ð7øÿúÿîxï4rð?rø�ú�ïî Ùî#î*$î.Ÿî1Gÿ�������À��������TVm$������������������������������COMMONMBUSSPECIFICATIONS246+w32BA5+w1ABABABABABAB0PhaseCycleBAw cycles(w>=0)requestor: MnRq _ FALSE;arbiter: MnGnt _ FALSE;4+warbiter: MnGnt _ TRUE;Figure 9. Timing for IOWriteFlowmaster: {MCmd _ IOWriteFlow; MAddr _ IOAddress; MnAdCycle _ FALSE}master: {MnAdCycle _ TRUE; MData _ IOData}slave: MnAdCycle=FALSE => MCmd#Done;slave: {MCmd _ Done; MAddr _ mumble; MnAdCycle _ FALSE}master: {MData _ IOData; MnRq _ TRUE} slave: MnAdCycle _ TRUE;FORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE}øÿúÿîéï.îéï@e�îéïD×�î wï,òþA�$î”ï-€�î”ï/¹�î[ï*Ýþ�$)îÍï*Ýþ�$)îéï3îéïIH�î”ï4+�î”ï1ò�î wï1dþA�$î”ï8�î”ï6d�î wï5ÖþA�$î”ï=�î”ï:Ö�î wï:HþA�$î”ïA�î”ï?H�î wï>ºþA�$î”ïEó�î”ïCº�î wïC,þA�$î”ïJe�î”ïH,�î wïGžþA�$î wïLþA�$îéïMº�î éïQžî"ïS×þDæ�$î"ïP‚þDæ�$îÍïQžî”ïLž�î”ïN×�~îÍï=VîÍï;¬îxïOîxïJ¬}îéï7~ø�ú�îxï0H}øÿúÿî Íï ¹~îxïF:ðBîxïAÈð*ø�ú�îxï=Vð$îxï8äð7îxï4rð>rïî Ùî#î*$î.Ÿî1G�������Ð��������TVm$����������������������COMMONMBUSSPECIFICATIONS256+w32BA5+w1ABABABABABAB0PhaseCycleBA(w>=0)w cycles4+warbiter: MnGnt _ FALSE;requestor: MnRq _ FALSE;arbiter: MnGnt _ TRUE;master: {MCmd _ IOReadFlow; MAddr _ IOAddress; MnAdCycle _ FALSE}master: MnAdCycle _ TRUE;slave: MnAdCycle _ FALSE => MCmd#Done;slave: {MCmd _ Done; MAddr _ mumble; MnAdCycle _ FALSE}Figure 10. Timing for MapRef and MapRefDirtymaster: {MnRq _TRUE; MnAdCycle _ TRUE}FORINTERNALXEROXUSEONLY��qïgî}�rî {ïg�ïgî!Wqî%©ïg�ïgî'ƒ�rî(kïg�ïgî)P�qî*Ãïg�rïgî+ŠvïgîE}øÿúÿîéï.îéï@e�îéïD×�î wï,òþA�$î”ï-€�î”ï/¹�î[ï*Ýþ�$)îÍï*Ýþ�$)îéï3îéïIH�î”ï4+�î”ï1ò�î wï1dþA�$î”ï8�î”ï6d�î wï5ÖþA�$î”ï=�î”ï:Ö�î wï:HþA�$î”ïA�î”ï?H�î wï>ºþA�$î”ïEó�î”ïCº�î wïC,þA�$î”ïJe�î”ïH,�î wïGžþA�$î wïLþA�$îéïMº�î éïQžî"ïS×þDæ�$î"ïP‚þDæ�$îÍïQžî”ïLž�î”ïN×�~îÍï;¬îÍï=V}îéï7~îxïJ¬îxïOø�ú�îxï0øÿúÿîxïF:ðAø�ú�îxïAÈîxï=Vð&îxï9+ð7}øÿúÿî”ïÕð,~îxï4rð&rø�ú�ïî Ùî#î*$î.Ÿî1G�������´��������TVm$��������������������������������������������ÿ HELVETICA��������������� �ÿ HELVETICA������������ ����ÿMATH�����������������þŸ����ÿ TIMESROMAN����������þŸ��� �ÿ TIMESROMAN����������þY��� �ÿLOGO�����������������ü´����ÿ HELVETICA�����������þŸ����ÿMATH�����������������þæ����ÿ HELVETICA������������þŸ����ÿ HELVETICA������������þæ����ÿ HELVETICA�����������þ����ÿ HELVETICA�����������ý…����ÿ TIMESROMAN�����������þæ����ÿ TIMESROMAN�����������þŸ�����ÿ TIMESROMAN����������þŸ���������������������������������������������j���� ������������®�����X���&��¡���1� �Ç���:��s���B� �Ÿ���K��ï���W��²���c� �����l�����t��–���{�������c��������„��æ���ˆ��X���Š��»���Œ��¹���Ž����������’����”�������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������j/�—��•���žk©·��ÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿÿ[]<>commonmbusspecs.tioga����������������������������������������������������������"Friday, March 22, 1985 9:18 pm PST�����������������������������������������������������������������������������������������������������������������������������������������