Cluster2.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
McCreight, May 13, 1986 2:28:43 pm PDT
Barth, April 28, 1986 12:14:11 pm PDT
Curry, October 22, 1986 8:01:07 pm PDT
Don Curry October 31, 1986 9:08:06 am PST
DIRECTORY CacheOps, Core, CoreClasses, CoreFlat, Dragon, DragOpsCross, IFU2, LizardCache, LizardHeart, LizardLiver, Ports, Rosemary, RosemaryUser;
Cluster2: CEDAR DEFINITIONS
= BEGIN
nCacheLines:   NAT;
skipIFURejects:   BOOL;
skipEURejects:   BOOL;
fullEU:     BOOL;
fullIFU:     BOOL;
fullIFUCuts:    LIST OF Core.ROPE;
quickIFU:     BOOL;
lastKs:     KitchenSink;
Instances:  TYPE = {ifu, eu, eCache, iCache};
historySize: NAT = 20;
OpaqueKitchenSink:  TYPE = REF ANY;
KitchenSink:    TYPE = REF KitchenSinkRec;
KitchenSinkRec:   TYPE = RECORD [
controlPanel:    ControlPanel ← NIL,
log:      Core.STREAMNIL,
lizardSimulation:  LizardSimulation ← NIL,
rosemarySimulation:  Rosemary.Simulation ← NIL,
rosemaryStores:   LIST OF REF ANYNIL,
clusterIOPort:   Ports.Port ← NIL,
vm:      CacheOps.VirtualMemory ← NIL,
iCache:     CacheOps.Cache ← NIL,
eCache:     CacheOps.Cache ← NIL,
protCyclesAfterReject: CARDINAL ← 0,
ifuSimulation:   Rosemary.Simulation ← NIL,
ifuSimulationTruthPort: Ports.Port ← NIL,
ifuSimulationTestPort: Ports.Port ← NIL,
ifuDisplay:    RosemaryUser.RoseDisplay ← NIL,
euSimulation:   Rosemary.Simulation ← NIL,
euPort:     Ports.Port ← NIL,
euSimulationTruthPort: Ports.Port ← NIL,
euSimulationTestPort: Ports.Port ← NIL,
euReject:     CoreFlat.FlatWire ← NIL,
euDisplay:    RosemaryUser.RoseDisplay ← NIL,
diagnostics:    Core.ROPENIL,
cluster:     Core.CellType ← NIL,
flatCT:     ARRAY Instances OF CoreFlat.FlatCellType   ← ALL[NIL],
coreInsts:     ARRAY Instances OF CoreClasses.CellInstance  ← ALL[NIL],
stateTop:     ARRAY [0..historySize) OF ClusterState,
stateFull:     ARRAY [0..historySize) OF ClusterState ];
ClusterState: TYPE = RECORD [
refCy:  REF INT       ← NIL,
refPh:  REF Dragon.Phase    ← NIL,
data:  ARRAY Instances OF REF ANYALL[NIL] ];
LizardSimulation:  TYPE = REF LizardSimulationRec;
LizardSimulationRec: TYPE = RECORD [
processor:   LizardHeart.Processor ← NIL,
control:   LizardHeart.Control ← nextInst,
euCache:   LizardCache.CacheBase,
lastInstrOps:  LIST OF REF ANYNIL ]; -- RegStore, CacheTrans
ControlPanel:  TYPE = REF ControlPanelRec;
ControlPanelRec: TYPE = RECORD [
diagnostic:     Core.ROPENIL,
cycle:       INT ← 0,
slowFromCycle:    INT ← 10000000,
instrCount:     INT ← 0,
slowFromInstr:    INT ← 10000000,
phase:       Dragon.Phase ← a,
stopInPh:      ARRAY Dragon.Phase OF BOOLALL[TRUE],
repeatPhase:     BOOLFALSE,
sampleFullIFU:    BOOLTRUE,
proceedFromCompareTest: BOOLFALSE,
proceedFromCheckPort:  BOOLFALSE,
continueTestFromAbort: BOOLFALSE,
reset, resched:    BOOLFALSE,
enaECacheLog:    BOOLFALSE,
enaIFULog:     BOOLFALSE,
enaEULog:     BOOLFALSE,
lizardToo:     BOOLTRUE,
emulateBreakpoint:   BOOLTRUE,
randomSeed:     INT ← 0,
randomCycleLimit:   INT ← 0,
running:      BOOLFALSE,
msg:       Core.ROPENIL ];
StartNewLizard:   PROC [ m: REF -- CacheOps.VM -- ] RETURNS [ sim: LizardSimulation];
SuccessHalt:    ERROR;
Breakpoint:    SIGNAL;
DefaultCheckSynch: IFU2.CheckSynchProc;
CSProcRec:    TYPE = RECORD [proc: IFU2.CheckSynchProc];
csProcRec:    CSProcRec; -- for easy replacement
MakeCluster:   PROC RETURNS [ks: KitchenSink];
DoCluster:    PROC [ks: KitchenSink, diagnostic: Core.ROPENIL];
GetPublicBool:   PROC [ks: KitchenSink, signal: ATOM] RETURNS [value: BOOL];
SetPublicBool:   PROC [ks: KitchenSink, signal: ATOM, value: BOOL];
SetPublic:    PROC [ks: KitchenSink, signal: ATOM, value: REF ANY];
SetPublicAndSettle:  PROC [ks: KitchenSink, signal: ATOM, value: REF ANY];
END.