DIRECTORY CacheOps, Dragon, DragOpsCross, DragOpsCrossUtils, LizardCache, LizardHeart, LizardRosemary, SparseMemory; LizardRosemaryImpl: CEDAR PROGRAM IMPORTS CacheOps, LizardCache, LizardHeart, DragOpsCrossUtils, SparseMemory EXPORTS LizardRosemary = BEGIN OPEN LizardRosemary; LizardEUCacheFetchTrap: PROC [base: LizardCache.CacheBase, addr: LizardCache.Word, cycle: INT, noEffect: BOOL _ FALSE] RETURNS [data: LizardCache.Word, status: LizardCache.TrapIndex, rejectCycles: INT] -- Lizard.CacheFetchProc -- = BEGIN sim: Simulation = NARROW[base.data]; [data: data, status: status, rejectCycles: rejectCycles] _ sim.euCache.fetch[base: sim.euCache, addr: addr, cycle: cycle, noEffect: noEffect]; sim.lastInstrOps _ CONS[ NEW[CacheTransRec _ [ instr: sim.processor.stats.instructions, cmd: Fetch, -- might be FetchHold, we can't tell here addr: DragOpsCrossUtils.WordToCard[addr], data: DragOpsCrossUtils.WordToCard[data], fault: SELECT status FROM ALUCondFalse => none, EUPageFault => page, EUWriteFault => write, ENDCASE => ERROR ]], sim.lastInstrOps]; END; LizardEUCacheStoreTrap: PROC [base: LizardCache.CacheBase, addr: LizardCache.Word, data: LizardCache.Word, cycle: INT] RETURNS [old: LizardCache.Word, status: LizardCache.TrapIndex, rejectCycles: INT] -- Lizard.CacheStoreProc -- = BEGIN sim: Simulation = NARROW[base.data]; [old: old, status: status, rejectCycles: rejectCycles] _ sim.euCache.store[base: sim.euCache, addr: addr, data: data, cycle: cycle]; sim.lastInstrOps _ CONS[ NEW[CacheTransRec _ [ instr: sim.processor.stats.instructions, cmd: Store, addr: DragOpsCrossUtils.WordToCard[addr], data: DragOpsCrossUtils.WordToCard[data], fault: SELECT status FROM ALUCondFalse => none, EUPageFault => page, EUWriteFault => write, ENDCASE => ERROR ]], sim.lastInstrOps]; END; NoteChangedReg: PROC [data: REF, processor: LizardHeart.Processor, reg: DragOpsCross.ProcessorRegister, old,new: DragOpsCross.Word] -- LizardHeart.RegChangeProc -- = BEGIN sim: Simulation = NARROW[data]; sim.lastInstrOps _ CONS[ NEW[RegStoreRec _ [ instr: sim.processor.stats.instructions, reg: reg, data: DragOpsCrossUtils.WordToCard[new] ]], sim.lastInstrOps]; END; NoteInstDone: PROC [data: REF, processor: LizardHeart.Processor, newPC, rtnPC: DragOpsCross.Word, control: LizardHeart.Control, cycles: INT] -- LizardHeart.InstDoneProc -- = BEGIN sim: Simulation = NARROW[data]; sim.control _ control; END; StartNewLizard: PUBLIC PROC [ m: REF -- CacheOps.VM -- ] RETURNS [ sim: Simulation ] = BEGIN StoreWord: PROC [ addr, data: Dragon.Word, readOnly, dirty: BOOL _ FALSE, privateData: REF _ NIL ] = {SparseMemory.Store[base: lizardVM, index: DragOpsCrossUtils.CardToWord[addr], new: DragOpsCrossUtils.CardToWord[data]]}; lizardVM: SparseMemory.Base; lizardSharedVM: LizardCache.SharedBase; sim _ NEW[SimulationRec]; lizardVM _ SparseMemory.Create[]; lizardSharedVM _ LizardCache.NewBase[lizardVM]; CacheOps.EnumerateVirtualMemory[m, StoreWord]; -- initialize Lizard's memory sim.euCache _ LizardCache.NewCache[lizardSharedVM]; sim.processor _ LizardHeart.NewProcessor[ ifuCache: LizardCache.NewCache[lizardSharedVM], euCache: NEW[LizardCache.CacheBaseRep _ [ fetch: LizardEUCacheFetchTrap, store: LizardEUCacheStoreTrap, data: sim ]], logger: NEW[LizardHeart.ChangeLoggerRep _ [ data: sim, regChange: NoteChangedReg, instDone: NoteInstDone ]] ]; END; DoInstruction: PUBLIC PROC [ sim: Simulation ] = BEGIN LizardHeart.InstructionExecute[sim.processor]; END; SuccessHalt: PUBLIC ERROR = CODE; Breakpoint: PUBLIC SIGNAL = CODE; CheckSynch: PUBLIC PROC [ lizardSimRef: REF Simulation, clusterInst: ClusterInst ] RETURNS [deltaInstrCount: INT _ 1] -- LizardRosemary.CheckSynchProc -- = BEGIN retry: BOOL _ TRUE; WHILE retry DO retry _ FALSE; deltaInstrCount _ csProcRec.proc[lizardSimRef: lizardSimRef, clusterInst: clusterInst]; -- debugger might set retry to TRUE NULL; -- for breakpoints and what-have-you ENDLOOP; END; csProcRec: PUBLIC CSProcRec _ [NIL]; END. ΒLizardRosemaryImpl.mesa Copyright c 1984 by Xerox Corporation. All rights reserved. Last edited by McCreight, February 13, 1986 2:04:34 pm PST Herrmann, September 5, 1985 10:53:41 am PDT Κω˜šœ™Jšœ Οmœ1™žœ žœžœžœGžœΟcœ˜ηJšž˜Jšœžœ ˜$J˜šœ:˜:JšœS˜SJ˜—šœžœ˜šžœ˜Jšœ(˜(Jšœ  )˜5Jšœ)˜)Jšœ)˜)šœžœž˜Jšœ˜Jšœ˜Jšœ˜Jšžœž˜—Jšœ˜—Jšœ˜J˜—Jšžœ˜J˜—JšŸœžœVžœ˜všžœFžœ œ˜oJšž˜Jšœžœ ˜$J˜šœ8˜8JšœK˜KJ˜—šœžœ˜šžœ˜Jšœ(˜(Jšœ ˜ Jšœ)˜)Jšœ)˜)šœžœž˜Jšœ˜Jšœ˜Jšœ˜Jšžœž˜—Jšœ˜—Jšœ˜J˜—Jšžœ˜J˜—J˜šŸœžœžœe œ˜₯Jšž˜Jšœžœ˜šœžœ˜šžœ˜Jšœ(˜(Jšœ ˜ Jšœ'˜'Jšœ˜—Jšœ˜—J˜Jšžœ˜J˜J˜—š Ÿ œžœžœkžœ œ˜­Jšž˜Jšœžœ˜Jšœ˜Jšžœ˜J˜J˜—š Ÿœžœžœžœ œžœ˜VJšž˜J˜š Ÿ œžœ-žœžœžœžœ˜dJšœy˜yJ˜—Jšœ˜Jšœ'˜'J˜Jšœžœ˜J˜Jšœ!˜!Jšœ/˜/Jšœ/ ˜LJ˜Jšœ3˜3J˜šœ)˜)Jšœ/˜/šœ žœ˜)Jšœ˜Jšœ˜Jšœ ˜ Jšœ˜—šœžœ ˜+Jšœ ˜ Jšœ˜Jšœ˜J˜—Jšœ˜J˜—Jšžœ˜J˜J˜—šŸ œžœžœ˜0Jšž˜Jšœ.˜.Jšžœ˜J˜J˜—Jšœ žœžœžœ˜!Jšœ žœžœžœ˜!J˜šŸ œžœžœžœ(žœžœ $œ˜œJšž˜Jšœžœžœ˜šžœž˜Jšœžœ˜JšœX #˜{Jšžœ $˜*Jšžœ˜—Jšžœ˜—J˜Jšœ žœžœ˜$J˜Jšžœ˜—J˜—…—”O