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263168 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263424 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263428 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263432 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263436 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263440 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263444 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263448 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263484 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263488 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263476 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263480 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263452 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263492 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263496 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263500 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263504 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 263636 $dirty FALSE $sharedMaster FALSE $valid TRUE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] [$addr 0 $dirty FALSE $sharedMaster FALSE $valid FALSE ] ] $cycleNo 5379 $skipRejects FALSE $rejectCycles 7 $cmdAB NoOp $address 263639 $fetchData 1361248512 $storeData 0 $cmdType fetch $pageFault FALSE $writeFault FALSE $storeParity FALSE $storeParityErrorBA FALSE $storeParityErrorAB FALSE $firstBOfCmdBA FALSE $resetBA FALSE $resettingAB FALSE $dHoldBA FALSE $holdingAB FALSE $rejectedB FALSE ] ] "ifu" [$name "ifu" $class $nextInstance $sim $parent $leftChild $rightSibling $firstInternalNode $internalNodes $components "aReg" [$name "aReg" $class $nextInstance $sim $parent $leftChild $rightSibling $firstInternalNode $internalNodes $components NIL $interfaceNodes $props $type Real $expansion Leaf $realCellStuff FALSE 0 1 255 255 255 4 12 152 2 12 2 16 5981 1 0 0 TRUE [$xBusPos 25 $sBA 0 $lBA 1 $addBus0 152 $sum 152 $addBus1 0 ] ] "bReg" [$name "bReg" $class $nextInstance $sim $parent $leftChild $rightSibling $firstInternalNode $internalNodes $components NIL $interfaceNodes $props $type Real $expansion Leaf $realCellStuff FALSE 0 1 255 255 255 4 12 152 1 4 2 16 5981 0 0 0 TRUE [$xBusPos 17 $sBA 0 $lBA 1 $addBus0 152 $sum 152 $addBus1 0 ] ] "cReg" [$name "cReg" $class $nextInstance $sim $parent $leftChild $rightSibling $firstInternalNode $internalNodes $components NIL $interfaceNodes $props $type Real $expansion Leaf $realCellStuff FALSE 0 1 255 255 255 3 11 131 16 5981 0 0 0 0 0 TRUE [$sBA 0 $lBA 1 $sLimitAB 111 $sLimitBA 111 $addBus0 0 $sum 16 $addBus1 16 ] ] "decoder" [$name "decoder" $class $nextInstance $sim $parent $leftChild $rightSibling $firstInternalNode $internalNodes $components NIL $interfaceNodes $props $type Real $expansion Leaf $realCellStuff FALSE 16 5981 255 255 255 255 255 3 0 0 0 0 4 12 4 12 3 11 2 12 1 4 2 255 255 255 0 0 1 0 16 5981 1 0 152 152 131 0 11 6 2 0 0 0 6 131 0 0 0 0 0 0 0 0 1 2 0 0 0 1 1 0 0 3624 0 0 0 0 0 0 0 0 0 0 TRUE [$iDecoderLogRef $phALastFLAG FALSE $iLogged TRUE $instReadyAB FALSE $opNameAB dLast $opAB 255 $alphaAB 255 $betaAB 255 $gammaAB 255 $deltaAB 255 $lengthAB 3 $xAB 1054557 $pAB 1054557 $iStkOverflowAB FALSE $iStkEmptyAB TRUE $mTrapAB [$trapPC 0 $killPipe FALSE ] $mStateAB [$delayed FALSE $done FALSE $cycle 0 $rescheduleWaiting FALSE $inhibitTraps TRUE $exceptions epReject ] $ifuStatusControlAB [$reschedule nop $inhibit nop ] $instrCountAB 3624 $mStateBA [$delayed TRUE $done TRUE $cycle 0 $rescheduleWaiting FALSE $inhibitTraps TRUE $exceptions epReject ] $mInstrBA [$aReg [$s0 cBase $s1 zero ] $bReg [$s0 cBase $s1 zero ] $getNextMacro FALSE $xBSource pc $doMacroJump FALSE $cReg [$s0 aBase $s1 minus1 ] $lSource [$s0 l $s1 zero ] $sSource [$s0 s $s1 deltaS ] $deltaS 0 $xASource none $aluRtisK FALSE $aluOp Or $condSel False $condEffect macroTrap $dontBypass FALSE $iStackPostEffect none $iTrapPostEffect none $euCacheCmd NoOp $pipedPLSASpec pls $pushLevel3 FALSE ] $instReadyBA FALSE $gammaBA 255 $deltaBA 255 $lengthBA 3 $cBA 0 $pBA 1054557 $lBA 1 $sBA 0 $xBA 1054557 $deltaSBA 0 $branchBA 0 $trapPBA 0 $resetBA FALSE $rescheduleBA FALSE $iStkOverflowBA FALSE $pushPendingBA FALSE $popPendingBA FALSE $iTrapEffectPendingBA none $lev3RejectBA TRUE $lev3FaultBA None $ifuStatusControlBA [$reschedule nop $inhibit nop ] $dHoldBA FALSE $instrCountBA 3624 ] ] "fetcher" [$name "fetcher" $class $nextInstance $sim $parent $leftChild $rightSibling $firstInternalNode $internalNodes $components "array" [$name "array" $class $nextInstance $sim $parent $leftChild $rightSibling $firstInternalNode $internalNodes $components NIL $interfaceNodes $props $type Real $expansion Leaf $realCellStuff FALSE 4 1496 0 0 0 0 0 0 255 255 255 255 255 1 1 1 1 1 0 0 TRUE [$iBufWords 8 $noneValidB TRUE $validAB FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE $validBA FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE $byteBA 243 130 138 17 192 35 62 243 17 1 130 252 227 37 2 198 242 112 219 59 17 1 130 252 65 146 242 138 111 146 247 143 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] ] "control" [$name "control" $class $nextInstance $sim $parent $leftChild $rightSibling $firstInternalNode $internalNodes $components NIL $interfaceNodes $props $type Real $expansion Leaf $realCellStuff FALSE 3 0 0 0 0 16 5981 4 1496 0 0 1 0 1 0 0 0 0 0 0 255 1 1 1 1 1 0 0 0 0 TRUE [$pDataBA 263640 $pParityBA FALSE $pParityErrorAB FALSE $noRoomForMoreAB FALSE $state fetchingFirst fetchingFirst $newFetchBA FALSE $successfulFetchBA FALSE $preFetchPCWord 263640 263640 $firstByteOffset 1 1 ] ] NIL $interfaceNodes $props $type Real $expansion Nested $realCellStuff FALSE 255 255 255 255 255 3 0 0 0 0 16 5981 4 1496 0 1 0 0 1 0 0 0 0 0 0 0 0 0 TRUE [$container $mirror $schedFirst $schedLast $firstNeeded $locked FALSE $running FALSE $insideNodes $nextPerturbed $nextWasPerturbed $firstPerturbed $firstAffected ] ] "misc" [$name "misc" $class $nextInstance $sim $parent $leftChild $rightSibling $firstInternalNode $internalNodes $components NIL $interfaceNodes $props $type Real $expansion Leaf $realCellStuff FALSE 0 0 0 0 0 FALSE ] "pipe" [$name "pipe" $class $nextInstance $sim $parent $leftChild $rightSibling $firstInternalNode $internalNodes $components NIL $interfaceNodes $props $type Real $expansion Leaf $realCellStuff FALSE 16 5981 16 5981 1 0 152 152 131 0 11 6 2 0 0 0 6 131 0 0 0 0 0 0 0 1 2 0 0 16 5427 1 39064 33536 0 0 0 0 0 0 0 11 6 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 TRUE [$delayed1 [$a 152 $b 152 $ka 1054557 $aluLt aRam $aluRt bRam $store1 bRam $aluOp Or $condSel False $condOp macroTrap $result2 r1 $store3 s2 $euCache NoOp $result3 r2 $c 131 $iStackOp none $iTrapOp none $p 1054557 $l 1 $s 0 ] [$a 152 $b 152 $ka 1054557 $aluLt aRam $aluRt bRam $store1 bRam $aluOp Or $condSel False $condOp macroTrap $result2 r1 $store3 s2 $euCache NoOp $result3 r2 $c 131 $iStackOp none $iTrapOp none $p 1054557 $l 1 $s 0 ] $level1 [$a 152 $b 152 $ka 1054557 $aluLt aRam $aluRt bRam $store1 bRam $aluOp Or $condSel False $condOp macroTrap $result2 r1 $store3 s2 $euCache NoOp $result3 r2 $c 131 $iStackOp none $iTrapOp none $p 1054008 $l 1 $s 0 ] [$a 152 $b 152 $ka 1054557 $aluLt aRam $aluRt bRam $store1 bRam $aluOp Or $condSel False $condOp macroTrap $result2 r1 $store3 s2 $euCache NoOp $result3 r2 $c 131 $iStackOp none $iTrapOp none $p 1054008 $l 1 $s 0 ] $level2 [$aluOp Or $condSel False $condOp macroTrap $result2 r1 $store3 s2 $euCache NoOp $result3 r2 $c 131 $iStackOp none $iTrapOp none $p 1054006 $l 1 $s 4 ] [$aluOp Or $condSel False $condOp macroTrap $result2 r1 $store3 s2 $euCache NoOp $result3 r2 $c 131 $iStackOp none $iTrapOp none $p 1054006 $l 1 $s 4 ] $level3 [$euCache Store $result3 r2 $c 131 $iStackOp none $iTrapOp none $p 1054003 $l 1 $s 4 ] [$euCache Store $result3 r2 $c 131 $iStackOp none $iTrapOp none $p 1054003 $l 1 $s 4 ] $lastCycleDelayedBA TRUE $level3RejectingBA TRUE $killPipeBA FALSE $dHoldBA FALSE ] ] "stack" [$name "stack" $class $nextInstance $sim $parent $leftChild $rightSibling $firstInternalNode $internalNodes $components NIL $interfaceNodes $props $type Real $expansion Leaf $realCellStuff FALSE 0 0 0 1 0 152 131 16 5427 1 16 5981 0 0 0 0 0 0 0 0 0 0 0 TRUE [$iStk [$valid FALSE FALSE $p 0 $l 0 ] [$valid FALSE FALSE $p 1054003 $l 1 ] [$valid FALSE FALSE $p 1053932 $l 5 ] [$valid FALSE FALSE $p 0 $l 0 ] [$valid FALSE FALSE $p 0 $l 0 ] [$valid FALSE FALSE $p 0 $l 0 ] [$valid FALSE FALSE $p 0 $l 0 ] [$valid FALSE FALSE $p 0 $l 0 ] [$valid FALSE FALSE $p 0 $l 0 ] [$valid FALSE FALSE $p 0 $l 0 ] [$valid FALSE FALSE $p 0 $l 0 ] [$valid FALSE FALSE $p 0 $l 0 ] [$valid FALSE FALSE $p 0 $l 0 ] [$valid FALSE FALSE $p 0 $l 0 ] [$valid FALSE FALSE $p 0 $l 0 ] [$valid FALSE FALSE $p 0 $l 0 ] $pushYoungestA FALSE $popYoungestA FALSE $pushEldestA FALSE $popEldestA FALSE $wasEmpty TRUE ] ] NIL $interfaceNodes $props $type Real $expansion Nested $realCellStuff FALSE 39064 33536 0 0 0 0 0 11 6 1 0 0 0 0 0 1 1 0 4 1496 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 3624 TRUE [$container $mirror $schedFirst $schedLast $firstNeeded $locked FALSE $running FALSE $insideNodes $nextPerturbed $nextWasPerturbed $firstPerturbed $firstAffected ] ] NIL $interfaceNodes $props $type Real $expansion Nested $realCellStuff FALSE 1 1 0 3624 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRUE [$container $mirror $schedFirst $schedLast $firstNeeded $locked FALSE $running FALSE $insideNodes $nextPerturbed $nextWasPerturbed $firstPerturbed $firstAffected ] ] "ClusterTester" [$name "ClusterTester" $class $nextInstance $sim $parent $leftChild $rightSibling $firstInternalNode $internalNodes $components NIL $interfaceNodes $props $type Real $expansion Leaf $realCellStuff FALSE 1 1 0 3624 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRUE [$sim $tester $testee $testeeInitData $parms [$stopBefore FALSE $stopAfter FALSE ] $instructionsAsAny $instructionsAsWP 1 1 0 3624 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 $driveAsAny [$fill0 0 $IPRejectB FALSE $fill1 0 $EPRejectB FALSE $fill2 0 $InstrCountAB FALSE $fill3 0 $PhA FALSE $fill4 0 $PhB FALSE $fill5 0 $Vdd FALSE $fill6 0 $Gnd FALSE $fill7 0 $PadVdd FALSE $fill8 0 $PadGnd FALSE $fill9 0 $RescheduleAB FALSE $fill10 0 $ClusterError FALSE $fill11 0 $EPData FALSE $fill12 0 $EPParityB FALSE $fill13 0 $EPCmdA FALSE $fill14 0 $EPFaultB FALSE $fill15 0 $MDataBA FALSE $fill16 0 $MCmdBA FALSE $fill17 0 $MNShared FALSE $fill18 0 $MParityBA FALSE $fill19 0 $MNError FALSE $fill20 0 $MReadyBA FALSE $fill21 0 $M1Rq FALSE $fill22 0 $M2Rq FALSE $fill23 0 $MNewRq FALSE $fill24 0 $M1Gnt FALSE $fill25 0 $M2Gnt FALSE $fill26 0 $ResetAB FALSE $fill27 0 $DHoldAB FALSE $fill28 0 $DShiftAB FALSE $fill29 0 $DExecuteAB FALSE $fill30 0 $DNSelectAB FALSE $fill31 0 $DDataInAB FALSE $fill32 0 $DDataOutAB FALSE ] $driveAsPtr $first FALSE $stateToo FALSE ] ] NIL $interfaceNodes $props $type Real $expansion Nested $realCellStuff FALSE TRUE [$container $mirror $schedFirst $schedLast $firstNeeded $locked FALSE $running FALSE $insideNodes $nextPerturbed $nextWasPerturbed $firstPerturbed $firstAffected ] ] [$cycle 5380 $slowFromCycle 7000 $instrCount 3624 $slowFromInstr 10000000 $phase b $stopInPh TRUE TRUE $repeatPhase FALSE $continueTestFromAbort FALSE $reset FALSE $resched FALSE $enaECacheLog TRUE $enaIDecoderLog TRUE $enaEULog TRUE $lizardToo TRUE $randomSeed 0 $randomCycleLimit 7000 $lizardDeltaIC -3 $ckptAtCycle 5380 $ckptEveryNCycles 0 $ckpt FALSE $rollbk FALSE $ckptFile "random.ckpt" $errMsg "Checkpointing..." ] [$lizardToo TRUE $lizardLastCyc 5870 $rejectedEU TRUE $eCmd Store $newECmd FALSE $addr 524593 $data 0 ]