LizardRosemaryImpl.mesa
Copyright © 1984 by Xerox Corporation. All rights reserved.
Last edited by McCreight, February 13, 1986 2:04:34 pm PST
Herrmann, September 5, 1985 10:53:41 am PDT
DIRECTORY
CacheOps,
Dragon,
DragOpsCross,
DragOpsCrossUtils,
LizardCache,
LizardHeart,
LizardRosemary,
SparseMemory;
LizardRosemaryImpl: CEDAR PROGRAM
IMPORTS CacheOps, LizardCache, LizardHeart, DragOpsCrossUtils, SparseMemory
EXPORTS LizardRosemary =
BEGIN OPEN LizardRosemary;
LizardEUCacheFetchTrap: PROC [base: LizardCache.CacheBase, addr: LizardCache.Word, cycle: INT, noEffect: BOOL ← FALSE] RETURNS [data: LizardCache.Word, status: LizardCache.TrapIndex, rejectCycles: INT] -- Lizard.CacheFetchProc -- =
BEGIN
sim: Simulation = NARROW[base.data];
[data: data, status: status, rejectCycles: rejectCycles] ←
sim.euCache.fetch[base: sim.euCache, addr: addr, cycle: cycle, noEffect: noEffect];
sim.lastInstrOps ← CONS[
NEW[CacheTransRec ← [
instr: sim.processor.stats.instructions,
cmd: Fetch, -- might be FetchHold, we can't tell here
addr: DragOpsCrossUtils.WordToCard[addr],
data: DragOpsCrossUtils.WordToCard[data],
fault: SELECT status FROM
ALUCondFalse => none,
EUPageFault => page,
EUWriteFault => write,
ENDCASE => ERROR
]],
sim.lastInstrOps];
END;
LizardEUCacheStoreTrap: PROC [base: LizardCache.CacheBase, addr: LizardCache.Word, data: LizardCache.Word, cycle: INT]
RETURNS [old: LizardCache.Word, status: LizardCache.TrapIndex, rejectCycles: INT] -- Lizard.CacheStoreProc -- =
BEGIN
sim: Simulation = NARROW[base.data];
[old: old, status: status, rejectCycles: rejectCycles] ←
sim.euCache.store[base: sim.euCache, addr: addr, data: data, cycle: cycle];
sim.lastInstrOps ← CONS[
NEW[CacheTransRec ← [
instr: sim.processor.stats.instructions,
cmd: Store,
addr: DragOpsCrossUtils.WordToCard[addr],
data: DragOpsCrossUtils.WordToCard[data],
fault: SELECT status FROM
ALUCondFalse => none,
EUPageFault => page,
EUWriteFault => write,
ENDCASE => ERROR
]],
sim.lastInstrOps];
END;
NoteChangedReg: PROC [data: REF, processor: LizardHeart.Processor, reg: DragOpsCross.ProcessorRegister, old,new: DragOpsCross.Word] -- LizardHeart.RegChangeProc -- =
BEGIN
sim: Simulation = NARROW[data];
sim.lastInstrOps ← CONS[
NEW[RegStoreRec ← [
instr: sim.processor.stats.instructions,
reg: reg,
data: DragOpsCrossUtils.WordToCard[new]
]],
sim.lastInstrOps];
END;
NoteInstDone: PROC [data: REF, processor: LizardHeart.Processor, newPC, rtnPC: DragOpsCross.Word, control: LizardHeart.Control, cycles: INT] -- LizardHeart.InstDoneProc -- =
BEGIN
sim: Simulation = NARROW[data];
sim.control ← control;
END;
StartNewLizard: PUBLIC PROC [ m: REF -- CacheOps.VM -- ] RETURNS [ sim: Simulation ] =
BEGIN
StoreWord: PROC [ addr, data: Dragon.Word, readOnly, dirty: BOOL ← FALSE, privateData: REF ← NIL ] =
{SparseMemory.Store[base: lizardVM, index: DragOpsCrossUtils.CardToWord[addr], new: DragOpsCrossUtils.CardToWord[data]]};
lizardVM: SparseMemory.Base;
lizardSharedVM: LizardCache.SharedBase;
sim ← NEW[SimulationRec];
lizardVM ← SparseMemory.Create[];
lizardSharedVM ← LizardCache.NewBase[lizardVM];
CacheOps.EnumerateVirtualMemory[m, StoreWord]; -- initialize Lizard's memory
sim.euCache ← LizardCache.NewCache[lizardSharedVM];
sim.processor ← LizardHeart.NewProcessor[
ifuCache: LizardCache.NewCache[lizardSharedVM],
euCache: NEW[LizardCache.CacheBaseRep ← [
fetch: LizardEUCacheFetchTrap,
store: LizardEUCacheStoreTrap,
data: sim
]],
logger: NEW[LizardHeart.ChangeLoggerRep ← [
data: sim,
regChange: NoteChangedReg,
instDone: NoteInstDone
]]
];
END;
DoInstruction: PUBLIC PROC [ sim: Simulation ] =
BEGIN
LizardHeart.InstructionExecute[sim.processor];
END;
SuccessHalt: PUBLIC ERROR = CODE;
Breakpoint: PUBLIC SIGNAL = CODE;
CheckSynch: PUBLIC PROC [ lizardSimRef: REF Simulation, clusterInst: ClusterInst ] RETURNS [deltaInstrCount: INT ← 1] -- LizardRosemary.CheckSynchProc -- =
BEGIN
retry: BOOL ← TRUE;
WHILE retry DO
retry ← FALSE;
deltaInstrCount ← csProcRec.proc[lizardSimRef: lizardSimRef, clusterInst: clusterInst]; -- debugger might set retry to TRUE
NULL; -- for breakpoints and what-have-you
ENDLOOP;
END;
csProcRec: PUBLIC CSProcRec ← [NIL];
END.