I interface
K: INT[32]; -- a, b, and c ram addresses are multiplexed on K. a=[0..7], b=[8..15], c=[16..23], addresses during PhiA, data during PhiB, data direction is EU -> IFU if the c address=161(decimal) during the previous PhiA, otherwise it is IFU -> EU.
The following signals should change during PhiB and be stable during PhiA.
AluBK: BOOL; -- b input of alu multiplexor control
R3R2: BOOL; -- multiplexor control on R2
R1AluA, R3AluA, R1AluB, R3AluB, R1S1, R3S1, R3R2, R3S3: BOOL; -- bypass control
The following signals are latched by the EU at the end of PhiB and are used on the next cycle.
AluOp: Mnemonic["AluOps"];
CondSelComp: BOOL; -- complement selected condition before trap decision
CondSelect: Mnemonic["CondSelects"];
Trap: BOOL; -- if selected condition is true then trap
Condition: BOOL; -- selected condition sent to IFU during second following PhiA after the PhiB that the previous signals were sent
WriteEuToCache: BOOL; -- generated by IFU in the PhA cycle during which the write command goes to the EU cache