DIRECTORY Cache2, CacheOps, Commander, Core, CoreClasses, CoreCreate, CoreOps, CoreProperties, Dragon, DragOpsCross, DragonRosemary, Ports, Random, Rosemary; Cache2Impl: CEDAR PROGRAM IMPORTS CacheOps, Commander, CoreClasses, CoreCreate, CoreOps, CoreProperties, DragonRosemary, Ports, Random, Rosemary EXPORTS Cache2 = BEGIN CacheName: ROPE = Rosemary.Register[roseClassName: "Cache", init: CacheInit, evalSimple: CacheSimple]; ROPE: TYPE = Core.ROPE; CellType: TYPE = Core.CellType; PI: TYPE = Cache2.PI; CacheState: TYPE = Cache2.CacheState; PortData: TYPE = RECORD [ name: Core.ROPE, width: NAT _ 1 ]; CacheParm: TYPE = RECORD [ vm: CacheOps.VirtualMemory, nLines: NAT, skipRejects: BOOL _ FALSE ]; randomSeed: INT _ -1; pITypes: ARRAY PI OF PortData _ [ PhA: ["PhA"], PhB: ["PhB"], PData: ["PData", 32], PCmdA: ["PCmdA", 8], PRejectB: ["PRejectB"], PUserMode: ["PUserMode"], PFaultB: ["PFaultB", 4], ResetAB: ["ResetAB"] ]; CacheInit: PROC -- Rosemary.InitProc [cellType: Core.CellType, p: Ports.Port, oldStateAny: REF ANY _ NIL, steady: BOOL _ FALSE ] RETURNS [stateAny: REF ANY _ NIL ] = { cp: REF CacheParm = NARROW[CoreProperties.GetCellTypeProp[cellType, $ClusterInfo]]; stateAny _ NEW[CacheState _ [ cache: CacheOps.NewCache[cp.vm, cp.nLines], skipRejects: cp.skipRejects ]]}; KernelMemoryRange: PROC [addr: Dragon.HexWord] RETURNS [inRange: BOOL] = {inRange _ addr IN [Dragon.HexWord[0]..DragOpsCross.KernalLimit]}; KernelIORange: PROC [addr: Dragon.HexWord] RETURNS [inRange: BOOL] = {inRange _ addr IN [Dragon.HexWord[0]..DragOpsCross.KernalLimit]}; CacheSimple: PROC [ p: Ports.Port, stateAny: REF ANY ] = {-- Rosemary.EvalProc -- state: REF CacheState = NARROW[stateAny]; PhA: BOOL = p[PI[PhA].ORD].b; PhB: BOOL = p[PI[PhB].ORD].b; IF PhA THEN { IF NOT state.phALast AND state.rejectCycles=0 AND state.fault = none THEN SELECT state.cmdType FROM store => CacheOps.Write[state.cache, state.address, state.storeDataBA]; specialFetch => CacheOps.Write[state.cache, state.address, state.csNew]; ioStore => SELECT state.address FROM 0 => state.csPredicted _ state.storeDataBA; 1 => state.csNew _ state.storeDataBA; ENDCASE => ERROR; ENDCASE; state.phALast _ TRUE; IF state.rejectCycles=0 THEN state.address _ p[PI[PData].ORD].lc; state.cmdAB _ VAL[p[PI[PCmdA].ORD].c]}; IF PhB THEN { IF state.phALast THEN { IF p[PI[ResetAB].ORD].b THEN { state.randomStream _ Random.Create[seed: randomSeed]; state.rejectCycles _ state.randomStream.ChooseInt[1, 5]; state.cmdType _ reset; state.cycleNo _ 0; state.cache _ CacheOps.NewCache[state.cache]; state.fault _ none } ELSE state.cycleNo _ state.cycleNo+1; IF state.rejectCycles=0 THEN { pageFault, writeFault: BOOL _ FALSE; state.fault _ none; SELECT state.cmdAB FROM NoOp => state.cmdType _ noOp; Fetch => { state.cmdType _ fetch; [data: state.fetchData, rejectCycles: state.rejectCycles, pageFault: pageFault] _ CacheOps.Access[state.cache, state.address, read, state.cycleNo]; IF pageFault THEN state.fault _ page }; FetchSpecial => { state.cmdType _ specialFetch; [data: state.fetchData, rejectCycles: state.rejectCycles, pageFault: pageFault] _ CacheOps.Access[state.cache, state.address, read, state.cycleNo]; SELECT TRUE FROM pageFault => state.fault _ page; state.fetchData # state.csPredicted => state.cmdType _ fetch; -- no write p[PI[PUserMode].ORD].b AND KernelMemoryRange[state.address] => state.fault _ memAccess; ENDCASE => { rc: INT; [data: state.fetchData, rejectCycles: rc, pageFault: pageFault, writeProtect: writeFault] _ CacheOps.Access[state.cache, state.address, write, state.cycleNo]; state.rejectCycles _ state.rejectCycles+rc; IF writeFault THEN state.fault _ write } }; Store => { state.cmdType _ store; IF p[PI[PUserMode].ORD].b AND KernelMemoryRange[state.address] THEN state.fault _ memAccess ELSE { [rejectCycles: state.rejectCycles, pageFault: pageFault, writeProtect: writeFault] _ CacheOps.Access[state.cache, state.address, write, state.cycleNo]; state.fault _ (SELECT TRUE FROM pageFault => page, writeFault => write, ENDCASE => none) } }; IOFetch => { state.cmdType _ fetch; SELECT state.address FROM 0 => state.fetchData _ state.csPredicted; 1 => state.fetchData _ state.csNew; ENDCASE => DragonRosemary.Assert [FALSE, "Cache doesn't yet implement IO operations" ]}; IOStore, IOStoreSpecial => { state.cmdType _ ioStore; IF state.address IN [0..1] THEN NULL -- store done above in next PhA ELSE IF p[PI[PUserMode].ORD].b AND KernelIORange[state.address] THEN state.fault _ ioAccess ELSE { DragonRosemary.Assert[FALSE, "IO addr not yet implemented" ]; state.fault _ ioAccess}}; ENDCASE => DragonRosemary.Assert[FALSE, "Cache doesn't implement this operation" ]; state.rejectCycles _ (SELECT TRUE FROM state.skipRejects => INT[0], state.rejectCycles>0 => state.rejectCycles+state.randomStream.ChooseInt[0, 1], ENDCASE => state.rejectCycles); IF state.fault#none THEN state.rejectCycles _ MAX[1, state.rejectCycles]; state.firstBOfCmdBA _ TRUE } ELSE { -- rejected on previous PhB DragonRosemary.Assert[ (state.cmdAB = NoOp) ]; state.rejectCycles _ state.rejectCycles-1; state.firstBOfCmdBA _ FALSE }; state.phALast _ FALSE }; SELECT state.cmdType FROM store, ioStore => IF state.firstBOfCmdBA THEN state.storeDataBA _ p[PI[PData].ORD].lc; specialFetch, fetch => IF state.rejectCycles=0 AND state.fault=none THEN p[PI[PData].ORD].lc_state.fetchData; ENDCASE => NULL}; -- neither write nor read PData p[PI[PData].ORD].d _ IF (PhB AND (state.cmdType=fetch OR state.cmdType=specialFetch) AND state.rejectCycles=0 AND state.fault = none) THEN drive ELSE none; p[PI[PFaultB].ORD].c _ Dragon.PBusFaults[(SELECT TRUE FROM NOT PhB => none, state.rejectCycles=1 => state.fault, ENDCASE => none)].ORD; p[PI[PRejectB].ORD].b _ PhB AND state.rejectCycles>0; p[PI[PFaultB].ORD].d _ p[PI[PRejectB].ORD].d _ IF PhA OR (PhB AND state.cmdType#noOp) THEN drive ELSE none }; Signal: SIGNAL = CODE; Cache: PUBLIC PROC [ vm: CacheOps.VirtualMemory, nLines: NAT _ CacheOps.StdLinesPerCache, skipRejects: BOOL _ FALSE ] RETURNS [ ct: CellType ] = { PIGet: PROC [ wireId: PI ] RETURNS [ w: Core.Wire ] = {w _ ct.public[wireId.ORD]}; wireList: LIST OF CoreCreate.WR _ NIL; FOR wireId: PI DECREASING IN PI DO wr: CoreCreate.WR _ (SELECT pITypes[wireId].width FROM 1 => pITypes[wireId].name, ENDCASE => CoreCreate.Seq[name: pITypes[wireId].name, size: pITypes[wireId].width]); wireList _ CONS[wr, wireList]; ENDLOOP; ct _ CoreOps.CreateCellType[ class: CoreClasses.unspecifiedCellClass, public: CoreCreate.WireList[wireList], props: CoreProperties.Props[[$ClusterInfo, NEW[CacheParm _ [ vm: vm, nLines: nLines, skipRejects: skipRejects ] ] ] ], name: "Cache" ]; [] _ Rosemary.BindCellType[cellType: ct, roseClassName: CacheName]; FOR wireId: PI IN PI DO [] _ Ports.InitPort[wire: ct.public[wireId.ORD], levelType: (SELECT pITypes[wireId].width FROM 1 => b, <=16 => c, <=32 => lc, ENDCASE => ERROR) ]; ENDLOOP}; Cache2CmdProc: PROC [cmd: Commander.Handle] -- Commander.CommandProc RETURNS [result: REF _ NIL, msg: Core.ROPE _ NIL] = {NULL}; Commander.Register["Cache2", Cache2CmdProc]; END. ÔCache2Impl.mesa Copyright c 1986 by Xerox Corporation. All rights reserved. McCreight, September 10, 1986 6:57:34 pm PDT Curry, September 27, 1986 1:11:45 pm PDT Don Curry October 30, 1986 5:09:53 pm PST Ê®˜šœ™Jšœ<™Jšœ˜šœ˜šœR˜RJšœD˜D—šœœœ˜Jšœ˜Jšœ˜Jšœ˜————šœ ˜ Jšœ˜šœ˜Jšœ)˜)Jšœ#˜#šœ˜ Jšœœ1˜7———šœ˜Jšœ˜šœœ˜JšœœŸ˜)šœœ œœ˜?Jšœ˜šœ˜Jšœœ"˜=Jšœ˜————Jšœœ-˜S—šœœœ˜&Jšœœ˜JšœN˜NJšœ˜—Jšœœœ˜IJšœœ˜—šœŸ˜"Jšœ.˜.Jšœ*˜*Jšœœ˜——Jšœœ˜—šœ˜Jšœ˜Jš œ œœœœ˜OJšœ ˜ Jš œ œœœœœ˜`JšœœŸ˜1——J˜šœœœ˜Jšœœœœœœœ˜†J˜—š œœ œœœ˜:Jšœ˜Jšœ$˜$Jšœœ˜—Jšœœ œ œ˜5š œœ œœ œ˜.Jš œœœœœ˜>—J˜—Jšžœœœ˜J˜šžœœœ'œ+œœœ˜’Jš žœœ œœ+œ˜SJš œ œœ œœ˜&š œ œ œœœ˜"šœœœ˜6Jšœ˜JšœM˜T—Jšœ œ˜Jšœ˜—šœ˜Jšœ(˜(Jšœ&˜&šœ+œ˜