--CachePRAMDriver.Mesa
--created by RoseTranslate from CachePRAMDriver.Rose of May 14, 1984 8:20:27 pm PDT for Barth.pa at May 14, 1984 8:23:43 pm PDT


DIRECTORY
RoseTypes, RoseCreate, BitOps, BitSwOps, Dragon, SwitchTypes;

CachePRAMDriver: CEDAR PROGRAM
IMPORTS RoseCreate, BitOps, BitSwOps, Dragon =

BEGIN OPEN
RoseTypes, BitOps, BitSwOps, Dragon;

--Signal Type decls


RegisterCells: PROC =
BEGIN
CreatePRAMDriverPorts[];
[] _ RoseCreate.RegisterCellClass[className: "PRAMDriver",
expandProc: NIL,
ioCreator: CreatePRAMDriverIO, initializer: InitializePRAMDriver,
evals: [EvalSimple: PRAMDriverEvalSimple],
blackBox: NIL, stateToo: NIL,
ports: PRAMDriverPorts,
drivePrototype: NEW [PRAMDriverDrive]];
END;

CreatePRAMDriverPorts: PROC = {PRAMDriverPorts _ RoseCreate.PortsFromFile["CachePRAMDriver.PRAMDriver.rosePorts"]};

PRAMDriverIORef: TYPE = REF PRAMDriverIORec;
PRAMDriverIORec: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0..32767],
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0..32767],
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0..32767],
LatchBias(2:15..15): BOOLEAN,
PBits(3:0..1055): PACKED ARRAY [0 .. 65] OF SwitchTypes.SwitchVal,
nPBits(69:0..1055): PACKED ARRAY [0 .. 65] OF SwitchTypes.SwitchVal,
fill5(135:0..14): [0..32767],
ShiftDataToMCtlPads(135:15..15): BOOLEAN,
PDataI(136:0..31): ARRAY [0..2) OF CARDINAL,
fill7(138:0..14): [0..32767],
PParityI(138:15..15): BOOLEAN,
fill8(139:0..14): [0..32767],
ShiftFeedBack(139:15..15): BOOLEAN,
fill9(140:0..14): [0..32767],
nShiftFeedBack(140:15..15): BOOLEAN,
fill10(141:0..14): [0..32767],
ShiftEqual(141:15..15): BOOLEAN,
fill11(142:0..14): [0..32767],
nShiftEqual(142:15..15): BOOLEAN,
fill12(143:0..14): [0..32767],
ShiftShift(143:15..15): BOOLEAN,
fill13(144:0..14): [0..32767],
nShiftShift(144:15..15): BOOLEAN,
fill14(145:0..14): [0..32767],
ShiftDataToPRAMDriver(145:15..15): BOOLEAN,
fill15(146:0..14): [0..32767],
nPBitsPrecharge(146:15..15): BOOLEAN,
fill16(147:0..14): [0..32767],
MuxRight(147:15..15): BOOLEAN,
fill17(148:0..14): [0..32767],
MuxLeft(148:15..15): BOOLEAN,
fill18(149:0..14): [0..32767],
PBitsDrive(149:15..15): BOOLEAN,
fill19(150:0..14): [0..32767],
nPBitsDrive(150:15..15): BOOLEAN,
fill20(151:0..14): [0..32767],
PRamRegToPDataI(151:15..15): BOOLEAN,
fill21(152:0..14): [0..32767],
nPRamRegToPDataI(152:15..15): BOOLEAN,
fill22(153:0..14): [0..32767],
SensePBits(153:15..15): BOOLEAN,
fill23(154:0..14): [0..32767],
SensePDataI(154:15..15): BOOLEAN,
fill24(155:0..14): [0..32767],
ParityIn(155:15..15): BOOLEAN,
fill25(156:0..14): [0..32767],
ParityOut(156:15..15): BOOLEAN,
fill26(157:0..14): [0..32767],
ReadPRAMReg(157:15..15): BOOLEAN,
fill27(158:0..14): [0..32767],
nReadPRAMReg(158:15..15): BOOLEAN];

-- port indices:
PRAMDriverPBitsPortIndex: CARDINAL = 3;
PRAMDriverNPBitsPortIndex: CARDINAL = 4;

PRAMDriverDrive: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0 .. 32768),
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0 .. 32768),
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0 .. 32768),
LatchBias(2:15..15): BOOLEAN,
fill3(3:0..14): [0 .. 32768),
PBits(3:15..15): BOOLEAN,
fill4(4:0..14): [0 .. 32768),
nPBits(4:15..15): BOOLEAN,
fill5(5:0..14): [0 .. 32768),
ShiftDataToMCtlPads(5:15..15): BOOLEAN,
fill6(6:0..14): [0 .. 32768),
PDataI(6:15..15): BOOLEAN,
fill7(7:0..14): [0 .. 32768),
PParityI(7:15..15): BOOLEAN,
fill8(8:0..14): [0 .. 32768),
ShiftFeedBack(8:15..15): BOOLEAN,
fill9(9:0..14): [0 .. 32768),
nShiftFeedBack(9:15..15): BOOLEAN,
fill10(10:0..14): [0 .. 32768),
ShiftEqual(10:15..15): BOOLEAN,
fill11(11:0..14): [0 .. 32768),
nShiftEqual(11:15..15): BOOLEAN,
fill12(12:0..14): [0 .. 32768),
ShiftShift(12:15..15): BOOLEAN,
fill13(13:0..14): [0 .. 32768),
nShiftShift(13:15..15): BOOLEAN,
fill14(14:0..14): [0 .. 32768),
ShiftDataToPRAMDriver(14:15..15): BOOLEAN,
fill15(15:0..14): [0 .. 32768),
nPBitsPrecharge(15:15..15): BOOLEAN,
fill16(16:0..14): [0 .. 32768),
MuxRight(16:15..15): BOOLEAN,
fill17(17:0..14): [0 .. 32768),
MuxLeft(17:15..15): BOOLEAN,
fill18(18:0..14): [0 .. 32768),
PBitsDrive(18:15..15): BOOLEAN,
fill19(19:0..14): [0 .. 32768),
nPBitsDrive(19:15..15): BOOLEAN,
fill20(20:0..14): [0 .. 32768),
PRamRegToPDataI(20:15..15): BOOLEAN,
fill21(21:0..14): [0 .. 32768),
nPRamRegToPDataI(21:15..15): BOOLEAN,
fill22(22:0..14): [0 .. 32768),
SensePBits(22:15..15): BOOLEAN,
fill23(23:0..14): [0 .. 32768),
SensePDataI(23:15..15): BOOLEAN,
fill24(24:0..14): [0 .. 32768),
ParityIn(24:15..15): BOOLEAN,
fill25(25:0..14): [0 .. 32768),
ParityOut(25:15..15): BOOLEAN,
fill26(26:0..14): [0 .. 32768),
ReadPRAMReg(26:15..15): BOOLEAN,
fill27(27:0..14): [0 .. 32768),
nReadPRAMReg(27:15..15): BOOLEAN];


PRAMDriverStateRef: TYPE = REF PRAMDriverStateRec;
PRAMDriverStateRec: TYPE = RECORD [
shiftData, nshiftData: BitDWord,
pRAMReg: BitDWord,
parityShift, nparityShift: BOOL,
pRAMRegParity: BOOL
];

CreatePRAMDriverIO: IOCreator = {
cell.realCellStuff.switchIO _ NEW [PRAMDriverIORec];
cell.realCellStuff.newIO _ NEW [PRAMDriverIORec];
cell.realCellStuff.oldIO _ NEW [PRAMDriverIORec];
};

InitializePRAMDriver: Initializer = {
IF leafily THEN
BEGIN
state: PRAMDriverStateRef _ NEW [PRAMDriverStateRec];
cell.realCellStuff.state _ state;
END;
};

PRAMDriverEvalSimple: CellProc =
BEGIN
sw: PRAMDriverIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: PRAMDriverIORef _ NARROW[cell.realCellStuff.newIO];
state: PRAMDriverStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN newIO, state;
Assert[NOT MoreThanOneOf[MuxRight, MuxLeft]];
Assert[NOT MoreThanOneOf[PBitsDrive, nPBitsDrive]];
Assert[NOT MoreThanOneOf[PRamRegToPDataI, nPRamRegToPDataI]];
Assert[NOT MoreThanOneOf[SensePBits, SensePDataI]];
Assert[NOT MoreThanOneOf[NOT nPBitsPrecharge, PBitsDrive]];
Assert[NOT MoreThanOneOf[PBitsDrive, SensePBits]];
Assert[NOT MoreThanOneOf[PRamRegToPDataI, SensePDataI]];
Assert[NOT MoreThanOneOf[ShiftFeedBack, ShiftShift, ReadPRAMReg]];
Assert[NOT MoreThanOneOf[ShiftFeedBack, nShiftFeedBack]];
Assert[NOT MoreThanOneOf[ShiftEqual, nShiftEqual]];
Assert[NOT MoreThanOneOf[ShiftShift, nShiftShift]];
Assert[NOT MoreThanOneOf[ReadPRAMReg, nReadPRAMReg]];
Assert[NOT ParityIn];

IF ShiftShift THEN {
nshiftData _ MDTD[DNOT[shiftData, 32], 32, 0, 31, nshiftData, 32, 1, 31];
nshiftData _ IBID[NOT ShiftDataToPRAMDriver, nshiftData, 32, 0];
nparityShift _ NOT EBFD[shiftData, 32, 31];
};
IF ShiftFeedBack THEN {
nshiftData _ MDTD[DNOT[shiftData, 32], 32, 0, 32, nshiftData, 32, 0, 32];
nparityShift _ NOT parityShift;
};
IF ShiftEqual THEN {
shiftData _ MDTD[DNOT[nshiftData, 32], 32, 0, 32, shiftData, 32, 0, 32];
ShiftDataToMCtlPads _ parityShift _ NOT nparityShift;
};
IF ShiftShift AND ShiftEqual THEN {
FOR i: CARDINAL IN [0..32) DO
shiftData _ IBID[ShiftDataToPRAMDriver, shiftData, 32, i];
ENDLOOP;
FOR i: CARDINAL IN [0..32) DO
nshiftData _ IBID[NOT ShiftDataToPRAMDriver, nshiftData, 32, i];
ENDLOOP;
parityShift _ ShiftDataToPRAMDriver;
nparityShift _ NOT ShiftDataToPRAMDriver;
};
IF SensePDataI THEN {
pRAMReg _ PDataI;
pRAMRegParity _ PParityI;
};
TRUSTED {
pbitd: SwitchMWord _ DESCRIPTOR[PBits];
npbitd: SwitchMWord _ DESCRIPTOR[nPBits];
s: SwitchTypes.Strength _ IF PBitsDrive THEN driveStrong ELSE none;
offset: CARDINAL _ IF MuxLeft THEN 0 ELSE 1;
FOR i:CARDINAL IN [0..32) DO
SIBIS[EBFD[pRAMReg, 32, i], pbitd, 66, (2*i)+offset, [[s, L], [s, H]]];
SIBIS[EBFD[pRAMReg, 32, i], npbitd, 66, (2*i)+offset, [[s, H], [s, L]]];
SIBIS[FALSE, pbitd, 66, (2*i)+1-offset, [[none, X], [none, X]]];
SIBIS[FALSE, npbitd, 66, (2*i)+1-offset, [[none, X], [none, X]]];
ENDLOOP;
SIBIS[pRAMRegParity, pbitd, 66, 64+offset, [[s, L], [s, H]]];
SIBIS[pRAMRegParity, npbitd, 66, 64+offset, [[s, H], [s, L]]];
SIBIS[FALSE, pbitd, 66, 65-offset, [[none, X], [none, X]]];
SIBIS[FALSE, npbitd, 66, 65-offset, [[none, X], [none, X]]];
IF NOT nPBitsPrecharge THEN {
SCDTS[BitDWordOnes, 32, 0, 32, pbitd, 66, 0, 32, [[none, X], [drive, H]]];
SCDTS[BitDWordOnes, 32, 0, 32, npbitd, 66, 0, 32, [[none, X], [drive, H]]];
SCDTS[BitDWordOnes, 32, 0, 32, pbitd, 66, 32, 32, [[none, X], [drive, H]]];
SCDTS[BitDWordOnes, 32, 0, 32, npbitd, 66, 32, 32, [[none, X], [drive, H]]];
SCWTS[BitWordOnes, 16, 0, 2, pbitd, 66, 64, 2, [[none, X], [drive, H]]];
SCWTS[BitWordOnes, 16, 0, 2, npbitd, 66, 64, 2, [[none, X], [drive, H]]];
};
IF SensePBits THEN {
FOR i:CARDINAL IN [0..32) DO
pRAMReg _ IBID[EBFS[pbitd, 66, (2*i)+offset], pRAMReg, 32, i];
ENDLOOP;
pRAMRegParity _ EBFS[pbitd, 66, 64+offset];
};
};
IF ReadPRAMReg THEN {
nshiftData _ DNOT[pRAMReg, 32];
nparityShift _ NOT pRAMRegParity;
};
ParityOut _ ParityIn;
FOR j:CARDINAL IN [0..32) DO
IF EBFD[pRAMReg, 32, j] THEN ParityOut _ NOT ParityOut;
ENDLOOP;
IF pRAMRegParity THEN ParityOut _ NOT ParityOut;
IF PRamRegToPDataI THEN {
PDataI _ pRAMReg;
PParityI _ pRAMRegParity;
};
END;
END;

PRAMDriverPorts: Ports _ NEW [PortsRep[28]];

RegisterCells[];

END.
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