--CachePCtl.Mesa
--created by RoseTranslate from CachePCtl.Rose of May 30, 1984 5:53:38 pm PDT for Barth.pa at May 30, 1984 5:53:53 pm PDT


DIRECTORY
RoseTypes, RoseCreate, BitOps, BitSwOps, Dragon, SwitchTypes;

CachePCtl: CEDAR PROGRAM
IMPORTS RoseCreate, BitOps, BitSwOps, Dragon =

BEGIN OPEN
RoseTypes, BitOps, BitSwOps, Dragon;

--Signal Type decls
PBusFaults: TYPE = Dragon.PBusFaults;
PBusCommands: TYPE = Dragon.PBusCommands;


RegisterCells: PROC =
BEGIN
CreatePCtlPorts[];
[] _ RoseCreate.RegisterCellClass[className: "PCtl",
expandProc: NIL,
ioCreator: CreatePCtlIO, initializer: InitializePCtl,
evals: [EvalSimple: PCtlEvalSimple],
blackBox: NIL, stateToo: NIL,
ports: PCtlPorts,
drivePrototype: NEW [PCtlDrive]];
END;

CreatePCtlPorts: PROC = {PCtlPorts _ RoseCreate.PortsFromFile["CachePCtl.PCtl.rosePorts"]};

PCtlIORef: TYPE = REF PCtlIORec;
PCtlIORec: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0..32767],
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0..32767],
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0..32767],
LatchBias(2:15..15): BOOLEAN,
fill3(3:0..14): [0..32767],
PhAb(3:15..15): BOOLEAN,
fill4(4:0..14): [0..32767],
PhBb(4:15..15): BOOLEAN,
fill5(5:0..14): [0..32767],
PhAh(5:15..15): BOOLEAN,
fill6(6:0..14): [0..32767],
PhBh(6:15..15): BOOLEAN,
fill7(7:0..14): [0..32767],
Resetb(7:15..15): BOOLEAN,
fill8(8:0..14): [0..32767],
nVirtualMatch(8:15..15): BOOLEAN,
fill9(9:0..14): [0..32767],
nMatchPageClean(9:15..15): BOOLEAN,
fill10(10:0..14): [0..32767],
nMatchCellShared(10:15..15): BOOLEAN,
fill11(11:0..14): [0..32767],
nMatchTIP(11:15..15): BOOLEAN,
fill12(12:0..14): [0..32767],
PAdrLow(12:15..15): BOOLEAN,
fill13(13:0..14): [0..32767],
nPAdrLow(13:15..15): BOOLEAN,
fill14(14:0..14): [0..32767],
PStore(14:15..15): BOOLEAN,
fill15(15:0..14): [0..32767],
MDoneAB(15:15..15): BOOLEAN,
fill16(16:0..14): [0..32767],
MHeldAB(16:15..15): BOOLEAN,
fill17(17:0..12): [0..8191],
MFaultAB(17:13..15): PBusFaults,
fill18(18:0..14): [0..32767],
PKillRequestB(18:15..15): BOOLEAN,
fill19(19:0..14): [0..32767],
PAdrHigh(19:15..15): BOOLEAN,
fill20(20:0..14): [0..32767],
PAdrLowToM(20:15..15): BOOLEAN,
fill21(21:0..11): [0..4095],
PCmdToMAB(21:12..15): PBusCommands,
fill22(22:0..14): [0..32767],
DoShiftBA(22:15..15): BOOLEAN,
fill23(23:0..14): [0..32767],
DoExecuteBA(23:15..15): BOOLEAN,
PDataI(24:0..31): ARRAY [0..2) OF CARDINAL,
fill25(26:0..14): [0..32767],
DrivePData(26:15..15): BOOLEAN,
fill26(27:0..14): [0..32767],
DrivePDataI(27:15..15): BOOLEAN,
fill27(28:0..11): [0..4095],
PCmdI(28:12..15): PBusCommands,
fill28(29:0..14): [0..32767],
PRejectDriveHigh(29:15..15): BOOLEAN,
fill29(30:0..14): [0..32767],
PRejectDriveLow(30:15..15): BOOLEAN,
fill30(31:0..14): [0..32767],
PFaultDrive(31:15..15): BOOLEAN,
fill31(32:0..12): [0..8191],
PFaultI(32:13..15): PBusFaults,
fill32(33:0..14): [0..32767],
PNPErrorDriveLow(33:15..15): BOOLEAN,
fill33(34:0..14): [0..32767],
ShiftFeedBack(34:15..15): BOOLEAN,
fill34(35:0..14): [0..32767],
nShiftFeedBack(35:15..15): BOOLEAN,
fill35(36:0..14): [0..32767],
ShiftEqual(36:15..15): BOOLEAN,
fill36(37:0..14): [0..32767],
nShiftEqual(37:15..15): BOOLEAN,
fill37(38:0..14): [0..32767],
ShiftShift(38:15..15): BOOLEAN,
fill38(39:0..14): [0..32767],
nShiftShift(39:15..15): BOOLEAN,
fill39(40:0..14): [0..32767],
ShiftDataToPCtl(40:15..15): BOOLEAN,
fill40(41:0..14): [0..32767],
ShiftDataToPRAMDriver(41:15..15): BOOLEAN,
fill41(42:0..14): [0..32767],
ShiftToEnable(42:15..15): BOOLEAN,
fill42(43:0..14): [0..32767],
ShiftToMustBeOne(43:15..15): BOOLEAN,
fill43(44:0..14): [0..32767],
PDataIToVAReg(44:15..15): BOOLEAN,
fill44(45:0..14): [0..32767],
ReadVAReg(45:15..15): BOOLEAN,
fill45(46:0..14): [0..32767],
nReadVAReg(46:15..15): BOOLEAN,
RequestMatch(47:0..15): SwitchTypes.SwitchVal,
fill47(48:0..14): [0..32767],
nPBitsPrecharge(48:15..15): BOOLEAN,
fill48(49:0..14): [0..32767],
MuxRight(49:15..15): BOOLEAN,
fill49(50:0..14): [0..32767],
MuxLeft(50:15..15): BOOLEAN,
fill50(51:0..14): [0..32767],
PBitsDrive(51:15..15): BOOLEAN,
fill51(52:0..14): [0..32767],
nPBitsDrive(52:15..15): BOOLEAN,
fill52(53:0..14): [0..32767],
PRamRegToPDataI(53:15..15): BOOLEAN,
fill53(54:0..14): [0..32767],
nPRamRegToPDataI(54:15..15): BOOLEAN,
fill54(55:0..14): [0..32767],
SensePBits(55:15..15): BOOLEAN,
fill55(56:0..14): [0..32767],
SensePDataI(56:15..15): BOOLEAN,
fill56(57:0..14): [0..32767],
ParityIn(57:15..15): BOOLEAN,
fill57(58:0..14): [0..32767],
ParityOut(58:15..15): BOOLEAN,
fill58(59:0..14): [0..32767],
ReadPRAMReg(59:15..15): BOOLEAN,
fill59(60:0..14): [0..32767],
nReadPRAMReg(60:15..15): BOOLEAN];

-- port indices:
PCtlRequestMatchPortIndex: CARDINAL = 46;

PCtlDrive: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0 .. 32768),
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0 .. 32768),
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0 .. 32768),
LatchBias(2:15..15): BOOLEAN,
fill3(3:0..14): [0 .. 32768),
PhAb(3:15..15): BOOLEAN,
fill4(4:0..14): [0 .. 32768),
PhBb(4:15..15): BOOLEAN,
fill5(5:0..14): [0 .. 32768),
PhAh(5:15..15): BOOLEAN,
fill6(6:0..14): [0 .. 32768),
PhBh(6:15..15): BOOLEAN,
fill7(7:0..14): [0 .. 32768),
Resetb(7:15..15): BOOLEAN,
fill8(8:0..14): [0 .. 32768),
nVirtualMatch(8:15..15): BOOLEAN,
fill9(9:0..14): [0 .. 32768),
nMatchPageClean(9:15..15): BOOLEAN,
fill10(10:0..14): [0 .. 32768),
nMatchCellShared(10:15..15): BOOLEAN,
fill11(11:0..14): [0 .. 32768),
nMatchTIP(11:15..15): BOOLEAN,
fill12(12:0..14): [0 .. 32768),
PAdrLow(12:15..15): BOOLEAN,
fill13(13:0..14): [0 .. 32768),
nPAdrLow(13:15..15): BOOLEAN,
fill14(14:0..14): [0 .. 32768),
PStore(14:15..15): BOOLEAN,
fill15(15:0..14): [0 .. 32768),
MDoneAB(15:15..15): BOOLEAN,
fill16(16:0..14): [0 .. 32768),
MHeldAB(16:15..15): BOOLEAN,
fill17(17:0..14): [0 .. 32768),
MFaultAB(17:15..15): BOOLEAN,
fill18(18:0..14): [0 .. 32768),
PKillRequestB(18:15..15): BOOLEAN,
fill19(19:0..14): [0 .. 32768),
PAdrHigh(19:15..15): BOOLEAN,
fill20(20:0..14): [0 .. 32768),
PAdrLowToM(20:15..15): BOOLEAN,
fill21(21:0..14): [0 .. 32768),
PCmdToMAB(21:15..15): BOOLEAN,
fill22(22:0..14): [0 .. 32768),
DoShiftBA(22:15..15): BOOLEAN,
fill23(23:0..14): [0 .. 32768),
DoExecuteBA(23:15..15): BOOLEAN,
fill24(24:0..14): [0 .. 32768),
PDataI(24:15..15): BOOLEAN,
fill25(25:0..14): [0 .. 32768),
DrivePData(25:15..15): BOOLEAN,
fill26(26:0..14): [0 .. 32768),
DrivePDataI(26:15..15): BOOLEAN,
fill27(27:0..14): [0 .. 32768),
PCmdI(27:15..15): BOOLEAN,
fill28(28:0..14): [0 .. 32768),
PRejectDriveHigh(28:15..15): BOOLEAN,
fill29(29:0..14): [0 .. 32768),
PRejectDriveLow(29:15..15): BOOLEAN,
fill30(30:0..14): [0 .. 32768),
PFaultDrive(30:15..15): BOOLEAN,
fill31(31:0..14): [0 .. 32768),
PFaultI(31:15..15): BOOLEAN,
fill32(32:0..14): [0 .. 32768),
PNPErrorDriveLow(32:15..15): BOOLEAN,
fill33(33:0..14): [0 .. 32768),
ShiftFeedBack(33:15..15): BOOLEAN,
fill34(34:0..14): [0 .. 32768),
nShiftFeedBack(34:15..15): BOOLEAN,
fill35(35:0..14): [0 .. 32768),
ShiftEqual(35:15..15): BOOLEAN,
fill36(36:0..14): [0 .. 32768),
nShiftEqual(36:15..15): BOOLEAN,
fill37(37:0..14): [0 .. 32768),
ShiftShift(37:15..15): BOOLEAN,
fill38(38:0..14): [0 .. 32768),
nShiftShift(38:15..15): BOOLEAN,
fill39(39:0..14): [0 .. 32768),
ShiftDataToPCtl(39:15..15): BOOLEAN,
fill40(40:0..14): [0 .. 32768),
ShiftDataToPRAMDriver(40:15..15): BOOLEAN,
fill41(41:0..14): [0 .. 32768),
ShiftToEnable(41:15..15): BOOLEAN,
fill42(42:0..14): [0 .. 32768),
ShiftToMustBeOne(42:15..15): BOOLEAN,
fill43(43:0..14): [0 .. 32768),
PDataIToVAReg(43:15..15): BOOLEAN,
fill44(44:0..14): [0 .. 32768),
ReadVAReg(44:15..15): BOOLEAN,
fill45(45:0..14): [0 .. 32768),
nReadVAReg(45:15..15): BOOLEAN,
fill46(46:0..14): [0 .. 32768),
RequestMatch(46:15..15): BOOLEAN,
fill47(47:0..14): [0 .. 32768),
nPBitsPrecharge(47:15..15): BOOLEAN,
fill48(48:0..14): [0 .. 32768),
MuxRight(48:15..15): BOOLEAN,
fill49(49:0..14): [0 .. 32768),
MuxLeft(49:15..15): BOOLEAN,
fill50(50:0..14): [0 .. 32768),
PBitsDrive(50:15..15): BOOLEAN,
fill51(51:0..14): [0 .. 32768),
nPBitsDrive(51:15..15): BOOLEAN,
fill52(52:0..14): [0 .. 32768),
PRamRegToPDataI(52:15..15): BOOLEAN,
fill53(53:0..14): [0 .. 32768),
nPRamRegToPDataI(53:15..15): BOOLEAN,
fill54(54:0..14): [0 .. 32768),
SensePBits(54:15..15): BOOLEAN,
fill55(55:0..14): [0 .. 32768),
SensePDataI(55:15..15): BOOLEAN,
fill56(56:0..14): [0 .. 32768),
ParityIn(56:15..15): BOOLEAN,
fill57(57:0..14): [0 .. 32768),
ParityOut(57:15..15): BOOLEAN,
fill58(58:0..14): [0 .. 32768),
ReadPRAMReg(58:15..15): BOOLEAN,
fill59(59:0..14): [0 .. 32768),
nReadPRAMReg(59:15..15): BOOLEAN];


PCtlStateRef: TYPE = REF PCtlStateRec;
PCtlStateRec: TYPE = RECORD [
pCmdLatch: PBusCommands,
pCmdShift, npCmdShift: BitWord,
rejectA, rejectB, parityError, parityErrorLatch: BOOL,
isNoOp, suppressVirtualAccess: BOOL,
rejectShift, nrejectShift, parityShift, nparityShift, requestShift, nrequestShift: BOOL,
loadEnable, nloadEnable, loadMustBeOne, nloadMustBeOne, readVA, nreadVA: BOOL,
pAdrLowShift, npAdrLowShift, pAdrHighShift, npAdrHighShift: BOOL,
requestMatch: BOOL,
ioReference, cacheStoreReference, cacheReference, fetchReference, storeReference, holdReference: BOOL,
shiftExecute, nShiftExecute: BOOL
];

CreatePCtlIO: IOCreator = {
cell.realCellStuff.switchIO _ NEW [PCtlIORec];
cell.realCellStuff.newIO _ NEW [PCtlIORec];
cell.realCellStuff.oldIO _ NEW [PCtlIORec];
};

InitializePCtl: Initializer = {
IF leafily THEN
BEGIN
state: PCtlStateRef _ NEW [PCtlStateRec];
cell.realCellStuff.state _ state;
END;
};

PCtlEvalSimple: CellProc =
BEGIN
sw: PCtlIORef _ NARROW[cell.realCellStuff.switchIO];
newIO: PCtlIORef _ NARROW[cell.realCellStuff.newIO];
state: PCtlStateRef _ NARROW[cell.realCellStuff.state];
BEGIN OPEN newIO, state;
Assert[NOT MoreThanOneOf[DoShiftBA, DoExecuteBA]];
requestMatch _ EBFSS[RequestMatch];
RequestMatch _ SIBISS[TRUE, RequestMatch, [[none, X], [driveWeak, H]]];
IF Resetb THEN {
pCmdLatch _ NoOp;
rejectA _ FALSE;
rejectB _ FALSE;
parityError _ FALSE;
parityErrorLatch _ FALSE;
};
PDataIToVAReg _ PhAh AND NOT rejectB;
IF PDataIToVAReg THEN {
pCmdLatch _ PCmdI;
PAdrHigh _ EBFD[PDataI, 32, 30];
PAdrLowToM _ EBFD[PDataI, 32, 31];
};

ioReference _ pCmdLatch=IOFetch OR pCmdLatch=IOStore OR pCmdLatch=IOFetchHold OR pCmdLatch=IOStoreHold;
cacheStoreReference _ pCmdLatch=Store OR pCmdLatch=StoreHold;
cacheReference _ pCmdLatch=Fetch OR pCmdLatch=FetchHold OR cacheStoreReference;
fetchReference _ pCmdLatch=Fetch OR pCmdLatch=FetchHold OR pCmdLatch=IOFetch OR pCmdLatch=IOFetchHold;
holdReference _ pCmdLatch=FetchHold OR pCmdLatch=StoreHold OR pCmdLatch=IOFetchHold OR pCmdLatch=IOStoreHold;
storeReference _ cacheStoreReference OR pCmdLatch=IOStore OR pCmdLatch=IOStoreHold;

IF PhBh THEN rejectB _ NOT MDoneAB AND requestMatch AND (ioReference OR (holdReference AND NOT MHeldAB) OR (cacheReference AND (nVirtualMatch OR NOT nMatchTIP)) OR (cacheStoreReference AND (NOT nMatchPageClean OR NOT nMatchCellShared)));
IF PhAb THEN nMatchTIP _ TRUE;
IF PhAh THEN rejectA _ rejectB;
IF PhBh THEN isNoOp _ pCmdLatch=NoOp;
PStore _ cacheStoreReference;
suppressVirtualAccess _ (pCmdLatch=StoreHold AND NOT MHeldAB) OR (NOT cacheReference);
PAdrLow _ NOT suppressVirtualAccess AND PAdrLowToM;
nPAdrLow _ NOT suppressVirtualAccess AND NOT PAdrLowToM;
PCmdToMAB _ pCmdLatch;
PKillRequestB _ NOT requestMatch;

PRejectDriveHigh _  PhBb AND requestMatch AND (rejectB OR (MDoneAB AND MFaultAB#None));
PRejectDriveLow _ PhAb;
PFaultDrive _ (PhBb AND requestMatch) OR PhAb;
PFaultI _ IF MDoneAB AND PhBb THEN MFaultAB ELSE None;

ParityIn _ FALSE;
IF PhAh THEN parityError _ ParityOut AND NOT rejectB AND NOT isNoOp;
IF PhBh AND parityError THEN parityErrorLatch _ TRUE;
PNPErrorDriveLow _ parityErrorLatch;

DrivePData _ PhBh AND requestMatch AND fetchReference;
DrivePDataI _ NOT DrivePData;

nPBitsPrecharge _ NOT PhAb;
MuxLeft _ NOT PAdrHigh OR ioReference;
MuxRight _ NOT MuxLeft;
PBitsDrive _ PhBh AND storeReference;
nPBitsDrive _ NOT PBitsDrive;
PRamRegToPDataI _ PhBh AND fetchReference;
nPRamRegToPDataI _ NOT PRamRegToPDataI;
SensePBits _ PRamRegToPDataI;
SensePDataI _ PhBh AND storeReference AND NOT rejectA;

ShiftEqual _ PhBb;
nShiftEqual _ NOT ShiftEqual;
ShiftFeedBack _ PhAb AND NOT (DoShiftBA OR DoExecuteBA);
nShiftFeedBack _ NOT ShiftFeedBack;
ShiftShift _ PhAb AND DoShiftBA;
nShiftShift _ NOT ShiftShift;
shiftExecute _ PhAb AND DoExecuteBA;
nShiftExecute _ NOT shiftExecute;

ShiftToEnable _ (shiftExecute AND loadEnable) OR Resetb;
ShiftToMustBeOne _ (shiftExecute AND loadMustBeOne) OR Resetb;
ReadVAReg _ shiftExecute AND readVA;
nReadVAReg _ NOT ReadVAReg;
ReadPRAMReg _ shiftExecute;
nReadPRAMReg _ nShiftExecute;
IF shiftExecute THEN {
npCmdShift _ WNOT[LOOPHOLE[pCmdLatch], 4];
nrejectShift _ rejectB;
nparityShift _ parityErrorLatch;
nrequestShift _ requestMatch;
npAdrLowShift _ PAdrLowToM;
npAdrHighShift _ PAdrHigh;
};

IF ShiftShift THEN {
nloadEnable _ NOT ShiftDataToPCtl;
nloadMustBeOne _ NOT loadEnable;
npCmdShift _ MWTW[WNOT[pCmdShift, 4], 4, 0, 3, npCmdShift, 4, 1, 3];
npCmdShift _ IBIW[NOT loadMustBeOne, npCmdShift, 4, 0];
nrejectShift _ NOT EBFW[pCmdShift, 4, 3];
nparityShift _ NOT rejectShift;
nrequestShift _ NOT parityShift;
nreadVA _ NOT requestShift;
npAdrLowShift _ NOT readVA;
npAdrHighShift _ NOT pAdrLowShift;
};
IF ShiftFeedBack THEN {
nloadEnable _ NOT loadEnable;
nloadMustBeOne _ NOT loadMustBeOne;
npCmdShift _ MWTW[WNOT[pCmdShift, 4], 4, 0, 4, npCmdShift, 4, 0, 4];
nrejectShift _ NOT rejectShift;
nparityShift _ NOT parityShift;
nrequestShift _ NOT requestShift;
nreadVA _ NOT readVA;
npAdrLowShift _ NOT pAdrLowShift;
npAdrHighShift _ NOT pAdrHighShift;
};
IF ShiftEqual THEN {
loadEnable _ NOT nloadEnable;
loadMustBeOne _ NOT nloadMustBeOne;
pCmdShift _ MWTW[WNOT[npCmdShift, 4], 4, 0, 4, pCmdShift, 4, 0, 4];
rejectShift _ NOT nrejectShift;
parityShift _ NOT nparityShift;
requestShift _ NOT nrequestShift;
readVA _ NOT nreadVA;
pAdrLowShift _ NOT npAdrLowShift;
pAdrHighShift _ NOT npAdrHighShift;
};
IF ShiftShift AND ShiftEqual THEN {
npAdrHighShift _ npAdrLowShift _ nreadVA _ nrequestShift _ nparityShift _ nrejectShift _ nloadMustBeOne _ nloadEnable _ NOT ShiftDataToPCtl;
FOR i: CARDINAL IN [0..4) DO
npCmdShift _ IBIW[nloadMustBeOne, npCmdShift, 4, i];
ENDLOOP;
pAdrHighShift _ pAdrLowShift _ readVA _ requestShift _ parityShift _ rejectShift _ loadMustBeOne _ loadEnable _ ShiftDataToPCtl;
FOR i: CARDINAL IN [0..4) DO
pCmdShift _ IBIW[loadMustBeOne, pCmdShift, 4, i];
ENDLOOP;
};

ShiftDataToPRAMDriver _ pAdrHighShift;
END;
END;

PCtlPorts: Ports _ NEW [PortsRep[60]];

RegisterCells[];

END.
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