DIRECTORY CacheMicroMachine; CacheMicroCodeB: CEDAR PROGRAM IMPORTS CacheMicroMachine = BEGIN OPEN CacheMicroMachine; Slave; Sequence[6]; -- DataTransport(0), IORead(5), IOReadDone(6), IOWrite(7), IOWriteDone(8), Reserve9(9), Reserve10(10), Reserve11(11), Reserve12(12), Reserve13(13), Reserve14(14), NoOp(15) Cycle[0, LIST[$MDataToMDataI, $MDataIToMatchReg, $MDataIToMAdrCtr, $MDataIToMRAMReg, $MDataIToFaults, $GetAdrRefresh, $PrechargeMNShared, $Done, $FlagLatch]]; Sequence[1]; -- ReadQuad(1) Cycle[0, LIST[$SampleRealMatch, $DriveShared, $SetShared, $SelRealData, $MAdrCtrToMAdr, $MBitsToMRAMReg, $MRAMRegToMDataI]]; Cycle[1, LIST[$DriveMData, $IncMAdrCtr, $MAdrCtrToMAdr, $SelRealData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]]; Cycle[2, LIST[$DriveMData, $IncMAdrCtr, $MAdrCtrToMAdr, $SelRealData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]]; Cycle[3, LIST[$DriveMData, $IncMAdrCtr, $MAdrCtrToMAdr, $SelRealData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]]; Cycle[4, LIST[$DriveMData, $CheckParity, $GetAdrRefresh, $Done, $ForceIdle]]; Sequence[2]; -- WriteQuad(2) Cycle[0, LIST[$ZeroMAdrCtr, $MAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData]]; Cycle[1, LIST[$IncMAdrCtr, $MAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData, $CheckParity]]; Cycle[2, LIST[$IncMAdrCtr, $MAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData, $CheckParity]]; Cycle[3, LIST[$IncMAdrCtr, $MAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData, $CheckParity, $DCheckParity, $GetAddress, $Done, $ForceIdle]]; Sequence[3]; -- WriteSingle(3) Cycle[0, LIST[$MAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData, $DCheckParity, $GetAddress, $Done, $ForceIdle, $ResetMaster]]; Sequence[4]; -- ChangeFlags(4) Cycle[0, LIST[$SelPageFlag, $RPDirtyVPValid, $Done, $ForceIdle]]; Master; Sequence[4]; -- IORead, real io operation Cycle[0, LIST[$GetAddress]]; Cycle[1, LIST[$DriveMCmd, $PageAccessToMDataI, $LowBitsAccessToMDataI, $MDataIToMData, $DriveMData, $Refresh, $Done, $ForceSlave, $ForceIdle]]; Cycle[2, LIST[$DriveMCmdToNoOp, $Refresh, $ReleaseMBus, $MDone, $SuppressPSample, $MRAMRegToPBits]]; Cycle[3, LIST[$DriveMCmdToNoOp, $Refresh, $Done, $SuppressPSample]]; -- this cycle is present because MDone could not be issued any earlier than cycle 2 and NextCmd must be issued at least 1 cycle after MDone to avoid servicing the same P bus request twice. Also the M bus could not be released any sooner and this cache must drive MCmd to a NoOp. Sequence[5]; -- IOWrite Cycle[0, LIST[$GetAddress]]; Cycle[1, LIST[$DriveMCmd, $PageAccessToMDataI, $LowBitsAccessToMDataI, $MDataIToMData, $DriveMData, $LeftPBitsToMRAMReg, $MRAMRegToMDataI, $Refresh, $Done, $ForceSlave, $ForceIdle, $DriveMDataDelayed]]; Cycle[2, LIST[$DriveMCmdToNoOp, $Refresh, $ReleaseMBus, $MDone, $SuppressPSample]]; Cycle[3, LIST[$DriveMCmdToNoOp, $Refresh, $Done, $SuppressPSample]]; -- this is here for the same reason as cycle 3 of IORead, real io operation. Sequence[6]; -- idle Cycle[0, LIST[$DriveMCmdToNoOp, $GetAdrRefresh, $Done]]; Cycle[1, LIST[$DriveMCmdToNoOp, $GetAdrRefresh, $Done]]; END. °CacheMicroCodeB.mesa Last Edited by: Barth, May 31, 1984 5:18:37 pm PDT The box which recodes MCmdIn can be made very simple if MBusCommands has 1 bit on for each of the commands interpreted by the slave, i.e. if ReadQuad, WriteQuad, WriteSingle, and ChangeFlags have one of the four bits on (or off, depending on whether the recoder inverts or not) and all other commands are classed by checking if more than one bit is on. ‌تظکJڑœ™J™2JکIcodeڑدk œکKکڑذbxœ‌œ‌کKڑ‌œک—KکKڑ‌œ‌œکKکKڑœà™àKککڑœ دc«ک¸Kڑœ ‌œ‘ک‍—ڑœ ںکKڑœ ‌œoک|Kڑœ ‌œkکxKڑœ ‌œkکxKڑœ ‌œkکxKڑœ ‌œ@کM—ڑœ ںکKڑœ ‌œaکnKڑœ ‌œnک{Kڑœ ‌œnک{Kڑœ ‌œ‌کھ—ڑœ ںکKڑœ ‌œگک‌—ڑœ ںکKڑœ ‌œ4کA——کڑœ ںک)Kڑœ ‌œکKڑœ ‌œ‚کڈKڑœ ‌œWکdKڑœ ‌œ9ں—کف—ڑœ ں کKڑœ ‌œکKڑœ ‌œ½کتKڑœ ‌œFکSKڑœ ‌œ9ںLک’—ڑœ ںکKڑœ ‌œ+ک8Kڑœ ‌œ+ک8——Kڑ‌œک—…—گ