Directory BitOps; Open BitOps; MCtlSequencer: CELL[ Vdd, GndBOOL, MFaultAB>EnumType["Dragon.PBusFaults"], PCmdToMABBOOL, MCmdInEnumType["Dragon.MBusCommands"], MCmdDrive>BOOL, MCmdDriveToDataTransport>BOOL, MCmdDriveToNoOp>BOOL, MNSharedSenseBABOOL, MNSharedDriveLow>BOOL, MNErrorDriveLow>BOOL, MReadySenseBOOL, MNewRqIBA>BOOL, MNewRqEnableBA>BOOL, MGntSenseBOOL, ParityOutBOOL, ShiftExecute, nShiftExecute>BOOL, CAMMDataIToMatchReg, CAMGetAdrRefresh, CAMGetAddress, CAMPageAccessToMDataI, CAMLowBitsAccessToMDataI, CAMAccessToMatch, CAMMatchToAccess, CAMVirtualAddressToAccess, CAMDriveCAMAccess>BOOL, RAMMDataIToMRAMReg, RAMMBitsToMRAMReg, RAMMRAMRegToMDataI, RAMMRAMRegToMBits, RAMMRAMRegToMBitsNoOrphan, RAMPBitsToMRAMReg, RAMLeftPBitsToMRAMReg, RAMMRAMRegToPBits>BOOL, FlagSetShared, FlagRPDirtyVPValid, FlagFlagLatch, FlagResetVPValid, FlagSetFlags, FlagSetTIP, FlagResetTIP, FlagResetMaster>BOOL, EntryMDataIToMAdrCtr, EntryGetAddress, EntryGetAdrRefresh, EntryRefresh, EntryMAdrCtrToMAdr, EntryIncMAdrCtr, EntryZeroMAdrCtr, EntryPAdrToMAdrCtr, EntryLowBitsAccessToMDataI, EntryLowBitsZeroToMDataI, EntrySelRealData, EntrySelPageFlag, EntrySelVictimData, EntrySelectVictimOrOrphan, EntryVirtualAccess, EntrynVirtualAccess, EntryShiftVictim, EntryFinishSharedStore>BOOL, GetAdrCmdBA>Mnemonic["GetAddressCommands"], GetAddressDoneBABOOL, IsNoOpBA, IsCleanBA, MatchRealBA>BOOL ] State holdTypeBA: BOOL, notHoldTypeBA: BOOL, pWantsM: BOOL, currentPDemandsBA, currentPDemandsAB: BitWord, -- this is actually an array of 7 bools, one per sequence needed. didRMBA, dirtyPageBA: BOOL, faultBitsAB: PBusFaults, mIdleAB, mIdleBA: BOOL, newRqAB, newRqBA: BOOL, mGntSenseAB, mRqAB: BOOL, holdingAB, holdingBA: BOOL, currentSequenceAB: BitWord, ioDoneAB: BOOL, parityErrorAB: BOOL, cycleShifterAB, cycleShifterBA: BitWord, -- sequence of 7 bits slaveAB: BOOL, forceSlaveBA: BOOL, driveMDataDelayedAB, dCheckParityAB, stopPipeAB: BOOL, parityBA: BOOL, mCmdOutAB, mCmdOutBA: MBusCommands, seqSenseSharedBA, seqMDoneBA, seqDoneBA, seqForceIdleBA, seqForceIdleAB, seqSenseReadyBA, seqMDataIToFaultsBA, seqCheckFaultsBA, seqDriveSharedBA, seqMDataIDriveBA, seqDriveMDataBA, seqDriveMDataDelayedBA, seqDriveMCmdBA, seqDriveMCmdToDataTransportBA, seqDriveMCmdToNoOpBA, seqDCheckParityBA, seqStopPipeNoReadyBA: BOOL, romSequence: BitWord, shiftData, nshiftData: BitDWord, phBLast: BOOL, pCAMMDataIToMatchReg, pCAMGetAdrRefresh, pCAMGetAddress, pCAMAccessToMatch, pCAMMatchToAccess, pCAMVirtualAddressToAccess, pCAMDriveCAMAccess: BOOL, pRAMMDataIToMRAMReg, pRAMMBitsToMRAMReg, pRAMMRAMRegToMDataI, pRAMMRAMRegToMBits, pRAMMRAMRegToMBitsNoOrphan, pRAMMRAMRegToPBits: BOOL, pFlagSetShared, pFlagRPDirtyVPValid, pFlagFlagLatch, pFlagSenseShared, pFlagResetVPValid, pFlagSetFlags, pFlagSetTIP, pFlagResetTIP, pFlagResetMaster:BOOL, pEntryFinishSharedStore:BOOL EvalSimple behaviour[cell]; ENDCELL; CEDAR behaviour: CellProc; RegisterBehaviour: PUBLIC PROC[b: CellProc]={ behaviour _ b}; ªCacheMCtlSequencer.rose Last edited by: Barth, May 31, 1984 6:02:55 pm PDT Timing and housekeeping interface Buffered timing and housekeeping interface Cell control P control <=> M control Debug interface Internal main memory interface More debug interface MRAMDriver interface Still more debug interface CAM control interface RAM control interface Flag control interface Entry control interface Control steel wool ʽ˜Jšœ™Jšœ2™2J˜J˜J˜ J˜šœÏkœ˜J˜šœ!™!Jšœ œ˜Jšœ œ˜—J™šœ*™*Jšœ œ˜Jšœ œ˜Jšœœ˜ —J˜™ Jšœ1œ˜6Jšœ$œ˜)—J˜™Jšœœ˜Jšœ'˜'Jšœ*˜*—J˜™Jšœ!œ˜&—J™šœ™Jšœœ˜Jšœ<œ˜AJšœ'˜'Jšœ*˜*Jšœ œ˜Jšœœ˜Jšœœ˜Jšœœ˜Jšœœ˜Jšœœ˜Jšœœ˜Jšœ œ˜Jšœœ˜ Jšœ œ˜Jšœœ˜Jšœ œ˜—J˜™JšœPœ˜U—J˜™Jšœ œ˜—J˜™Jšœœ˜Jšœœ˜Jšœœ˜!—J™™Jšœ¸œ˜½—J™™Jšœ¥œ˜ª—J˜™Jšœ|œ˜—J™™Jšœïœ˜ô—J˜™Jšœ+˜+Jšœœ˜Jšœœ˜Jšœ!˜%—Jšœ˜J˜˜Jšœ œ˜Jšœœ˜Jšœ œ˜Jšœ0ÏcA˜qJšœœ˜Jšœ˜Jšœœ˜Jšœœ˜Jšœœ˜Jšœœ˜J˜Jšœ œ˜Jšœœ˜Jšœ)ž˜>Jšœ œ˜Jšœœ˜Jšœ1œ˜6Jšœ œ˜Jšœ#˜#Jšœ¼œ˜ÁJ˜J˜ J˜Jšœ œ˜J˜Jšœœ˜”Jšœ‚œ˜‡Jšœ–˜›Jšœ˜—˜ Jšœ˜—Jšœ˜J˜š˜J˜J˜J˜šÏnœœœ˜-Jšœ˜—J˜——J˜—…— òY