MCtlRAMCtl CacheMCtlRAMCtl 0 NIL [Vdd<BOOL, Gnd<BOOL, LatchBias<BOOL, PhBb<BOOL, PAdrHigh<BOOL, DoHoldBA<BOOL, ShiftDataToMCtl<BOOL, ShiftEqual<BOOL, nShiftEqual<BOOL, ShiftFeedBack<BOOL, nShiftFeedBack<BOOL, ShiftShift<BOOL, nShiftShift<BOOL, nMBitsPrecharge>BOOL, MuxRight>BOOL, MuxLeft>BOOL, MBitsDrive>BOOL, nMBitsDrive>BOOL, MRamRegToMDataI>BOOL, nMRamRegToMDataI>BOOL, SenseMBits>BOOL, SenseMDataI>BOOL, ParityIn>BOOL, SensePBitsLeft>BOOL, SensePBitsRight>BOOL, DrivePBits>BOOL, nDrivePBits>BOOL, MRamRegToMBits>BOOL, nMRamRegToMBits>BOOL, ShiftToMBits>BOOL, nShiftToMBits>BOOL, MBitsToShift>BOOL, nMBitsToShift>BOOL, ShiftDataToFlagCtl>BOOL, ReadEntry<BOOL, WriteEntry<BOOL, ShiftExecute<BOOL, nShiftExecute<BOOL, RAMMDataIToMRAMReg<BOOL, RAMMBitsToMRAMReg<BOOL, RAMMRAMRegToMDataI<BOOL, RAMMRAMRegToMBits<BOOL, RAMMRAMRegToMBitsNoOrphan<BOOL, RAMPBitsToMRAMReg<BOOL, RAMLeftPBitsToMRAMReg<BOOL, RAMMRAMRegToPBits<BOOL, MatchRealBA<BOOL, MAdrHigh<BOOL] !!