Imports BitOps, Dragon; Open BitOps, Dragon; MCtlEntryCtl: CELL[ Vdd, GndINT[8], VirtualAccess, nVirtualAccess, SelCell, SelVictimAdr, SelMapAdr, SelRealData, SelPageFlag, SelVictimData, SelRealAdr>BOOL, FinishSharedStore>BOOL, MAdrLow, nMAdrLow>BOOL, VictimFeedback, nVictimFeedback, ShiftVictim, nShiftVictim>BOOL, ForceDataSelect>BOOL, PAdrHigh, PAdrLowToMBOOL, ReadEntry, WriteEntry>BOOL, ShiftExecute, nShiftExecuteBOOL, IsNoOpBA, MatchRealBA EBFW[mAdrCtrB, 2, 1], refreshCycle => EBFW[refreshCountB, 9, 8], ENDCASE => FALSE; -- don't really care what it is nMAdrLow _ NOT MAdrLow; MAdrHigh _ EBFW[mAdrCtrB, 2, 0]; IF EntryLowBitsAccessToMDataI THEN { MDataI _ IBID[PAdrHigh, MDataI, 32, 30]; MDataI _ IBID[PAdrLowToM, MDataI, 32, 31]; }; IF EntryLowBitsZeroToMDataI THEN MDataI _ ICID[0, MDataI, 32, 30, 2]; CellAdr _ IF DoExecuteBA THEN sCellAdr ELSE MWTW[refreshCountB, 9, 0, 8, 0, 8, 0, 8]; nCellAdr _ WNOT[CellAdr, 8]; IF refreshCycle THEN VirtualAccess _ EBFW[refreshCountB, 9, 8]; IF EntryVirtualAccess THEN VirtualAccess _ TRUE; IF addressCycle OR EntrynVirtualAccess THEN VirtualAccess _ FALSE; nVirtualAccess _ NOT VirtualAccess; ShiftVictim _ PhAh AND EntryShiftVictim; nShiftVictim _ NOT ShiftVictim; VictimFeedback _ PhAb AND (NOT EntryShiftVictim OR DoHoldBA); nVictimFeedback _ NOT VictimFeedback; ForceDataSelect _ PhAb AND Resetb; GetAddressDoneBA _ addressCycle; SelCell _ ShiftExecute OR (PhAb AND refreshCycle); SelVictimAdr _ PhAh AND ((addressCycle AND GetAdrCmdBA=VictimReal) OR (EntrySelectVictimOrOrphan AND NOT MatchRealBA AND NOT addressCycle)); SelMapAdr _ PhAh AND addressCycle AND GetAdrCmdBA=RefRealAssemble; SelRealData _ PhAh AND (EntrySelRealData OR (EntrySelectVictimOrOrphan AND MatchRealBA)); SelPageFlag _ PhAh AND EntrySelPageFlag; SelVictimData _ PhAh AND (EntrySelVictimData OR (EntrySelectVictimOrOrphan AND NOT MatchRealBA)); SelRealAdr _ PhAh AND EntrySelectVictimOrOrphan AND MatchRealBA AND NOT addressCycle; FinishSharedStore _ EntryFinishSharedStore; IF ShiftShift THEN { snMAdrLow _ NOT ShiftDataToEntryCtl; snMAdrHigh _ NOT sMAdrLow; snReadEntry _ NOT sMAdrHigh; snWriteEntry _ NOT sReadEntry; snCellAdr _ MWTW[WNOT[sCellAdr, 8], 8, 1, 7, snCellAdr, 8, 0, 7]; snCellAdr _ IBIW[NOT sWriteEntry, snCellAdr, 8, 7]; }; IF ShiftFeedBack THEN { snMAdrLow _ NOT sMAdrLow; snMAdrHigh _ NOT sMAdrHigh; snReadEntry _ NOT sReadEntry; snWriteEntry _ NOT sWriteEntry; snCellAdr _ WNOT[sCellAdr, 8]; }; IF ShiftEqual THEN { sMAdrLow _ NOT snMAdrLow; sMAdrHigh _ NOT snMAdrHigh; sReadEntry _ NOT snReadEntry; sWriteEntry _ NOT snWriteEntry; sCellAdr _ WNOT[snCellAdr, 8]; ShiftDataToCAMCtl _ EBFW[sCellAdr, 8, 0]; }; ReadEntry _ sReadEntry; WriteEntry _ sWriteEntry; ENDCELL RCacheMCtlEntryCtl.rose Last edited by: Barth, May 30, 1984 4:26:17 pm PDT Timing and housekeeping interface Buffered timing and housekeeping interface Cell control P control <=> M control Debug interface Internal main memory interface More debug interface Still more debug interface Entry control interface Control steel wool Ê ˜Jšœ™Jšœ2™2J˜Jšœ˜Jšœ˜J™šœÏkœ˜J˜šœ!™!Jšœ œ˜Jšœ œ˜—J™šœ*™*Jšœ œ˜Jšœ œ˜Jšœœ˜ —J˜™ Jšœœ˜Jšœuœ˜zJšœœ˜Jšœœ˜Jšœ:œ˜@Jšœœ˜—J™™Jšœœ˜—J˜™Jšœœ˜—J™šœ™Jšœœ˜—J˜™JšœPœ˜U—J˜™Jšœœ˜Jšœœ˜Jšœœ˜Jšœœ˜!—J˜™Jšœïœ˜ô—J˜™Jšœ+˜+Jšœœ˜ Jšœ˜—Jšœ˜J˜˜JšœœÏc ˜?Jšœœ˜'Jšœœ˜'Jšœ,œ˜1Jšœ˜Jšœ4œ˜9Jšœ˜ —˜ JšœœG˜QJšœœ/˜9Jšœœ)˜3Jšœœ)˜3šœœ˜Jšœ˜Jšœ˜J˜—šœœ˜Jšœœœœ ˜WJšœœœœž|˜Èšœœ˜Jšœ˜Jšœ"œ˜*Jšœ˜—šœ˜Jšœœ#œ˜BJšœ˜J˜—J˜—J˜Jš œœ œœœœ ˜[Jšœœœ˜8Jšœœ˜&šœœ˜Jšœ œ˜,Jšœ œ˜*J˜—Jš œœœœœœžP˜·šœ œœ˜Jšœœ˜+Jšœœ˜*Jšœœž˜2—Jšœ œ ˜Jšœ œ˜ šœœ˜$Jšœ œ˜(Jšœ œ˜*J˜—Jšœœ œ˜EJ˜Jš œ œ œ œœ%˜UJšœ œ ˜Jšœœœ˜?Jšœœœ˜0Jšœœœœ˜BJšœœ˜#Jšœœ˜(Jšœœ ˜Jšœœœœ ˜=Jšœœ˜%Jšœœ˜"Jšœ ˜ J™Jšœœœ˜2Jšœœœœœœ œœ˜Jšœœœ˜BJšœœœœ˜YJšœœ˜(Jš œœœœœ˜aJš œœœ œœ˜UJšœ+˜+J˜šœ œ˜Jšœ œ˜$Jšœ œ ˜Jšœœ ˜Jšœœ ˜Jšœ œœ,˜AJšœ œœ˜3J˜—šœœ˜Jšœ œ ˜Jšœ œ ˜Jšœœ ˜Jšœœ ˜Jšœ œ˜J˜—šœ œ˜Jšœ œ ˜Jšœ œ ˜Jšœ œ ˜Jšœœ˜Jšœ œ˜Jšœœ˜)J˜—Jšœ˜Jšœ˜—Jš˜—J˜—…—&˜