Directory Dragon; Library CacheMCtlSequencer, CacheMCtlEntryCtl, CacheMCtlFlagCtl, CacheMCtlRAMCtl, CacheMCtlCAMCtl; MCtl: CELL[ Vdd, GndINT[8], VirtualAccess, nVirtualAccess, SelCell, SelVictimAdr, SelMapAdr, SelRealData, SelPageFlag, SelVictimData, SelRealAdr>BOOL, FinishSharedStore>BOOL, VPValid, nVPValid, RPValid, nRPValid, RPDirty, nRPDirty, Master, nMaster, Shared, nShared, Victim, nVictim, TIP, nTIP, Broken, nBroken=BIT, MAdrLow, nMAdrLow>BOOL, VictimFeedback, nVictimFeedback, ShiftVictim, nShiftVictim>BOOL, ForceDataSelect>BOOL, MDoneAB, MHeldAB>BOOL, MFaultAB>EnumType["Dragon.PBusFaults"], PAdrHigh, PAdrLowToMBOOL, MCmdInEnumType["Dragon.MBusCommands"], MCmdDrive>BOOL, MCmdDriveToDataTransport>BOOL, MCmdDriveToNoOp>BOOL, MNSharedSenseBABOOL, MNSharedDriveLow>BOOL, MNErrorDriveLow>BOOL, MReadySenseBOOL, MNewRqIBA>BOOL, MNewRqEnableBA>BOOL, MGntSenseBOOL, ShiftEqual, nShiftEqual, ShiftFeedBack, nShiftFeedBack, ShiftShift, nShiftShift>BOOL, PageAccessToAccess, BlockAccessToAccess>BOOL, PageVirtualToAccess, BlockVirtualToAccess>BOOL, MatchToAccess>BOOL, MDataToMatch, AccessToMatch>BOOL, PageAccessToMData, nPageAccessToMData>BOOL, BlockAccessToMData, nBlockAccessToMData>BOOL, AccessToPageBlockAccess, nAccessToPageBlockAccess, ShiftToPageBlockAccess, nShiftToPageBlockAccess, AccessDrive, nAccessDrive>BOOL, PageBlockAccessToShift, nPageBlockAccessToShift>BOOL, nCAMAccessPrecharge>BOOL, nMBitsPrecharge, MuxRight, MuxLeft, MBitsDrive, nMBitsDrive, MRamRegToMDataI, nMRamRegToMDataI, SenseMBits, SenseMDataI, ParityIn>BOOL, ParityOutBOOL, MRamRegToMBits, nMRamRegToMBits>BOOL, ShiftToMBits, nShiftToMBits, MBitsToShift, nMBitsToShift>BOOL ] Expand ShiftDataToFlagCtl, ShiftDataToSequencer, ShiftDataToEntryCtl, ShiftDataToCAMCtl: BOOL; ShiftExecute, nShiftExecute: BOOL; ReadEntry, WriteEntry: BOOL; CAMMDataIToMatchReg, CAMGetAdrRefresh, CAMGetAddress, CAMPageAccessToMDataI, CAMLowBitsAccessToMDataI, CAMAccessToMatch, CAMMatchToAccess, CAMVirtualAddressToAccess, CAMDriveCAMAccess: BOOL; RAMMDataIToMRAMReg, RAMMBitsToMRAMReg, RAMMRAMRegToMDataI, RAMMRAMRegToMBits, RAMMRAMRegToMBitsNoOrphan, RAMPBitsToMRAMReg, RAMLeftPBitsToMRAMReg, RAMMRAMRegToPBits: BOOL; FlagSetShared, FlagRPDirtyVPValid, FlagFlagLatch, FlagResetVPValid, FlagSetFlags, FlagSetTIP, FlagResetTIP, FlagResetMaster: BOOL; EntryMDataIToMAdrCtr, EntryGetAddress, EntryGetAdrRefresh, EntryRefresh, EntryMAdrCtrToMAdr, EntryIncMAdrCtr, EntryZeroMAdrCtr, EntryPAdrToMAdrCtr, EntryLowBitsAccessToMDataI, EntryLowBitsZeroToMDataI, EntrySelRealData, EntrySelPageFlag, EntrySelVictimData, EntrySelectVictimOrOrphan, EntryVirtualAccess, EntrynVirtualAccess, EntryShiftVictim, EntryFinishSharedStore: BOOL; GetAdrCmdBA: Mnemonic["GetAddressCommands"]; GetAddressDoneBA: BOOL; LatchSharedAB: BOOL; IsNoOpBA, IsCleanBA, MatchRealBA: BOOL; MAdrHigh: BOOL; mCtlSequencer:MCtlSequencer[]; mCtlEntryCtl:MCtlEntryCtl[]; mCtlFlagCtl:MCtlFlagCtl[]; mCtlRAMCtl:MCtlRAMCtl[]; mCtlCAMCtl:MCtlCAMCtl[] ENDCELL ¶CacheMCtl.rose Last edited by: Barth, May 31, 1984 6:02:39 pm PDT Timing and housekeeping interface Buffered timing and housekeeping interface Cell control P control <=> M control Debug interface Internal main memory interface More debug interface MCAMDriver interface MRAMDriver interface Still more debug interface CAM control interface RAM control interface Flag control interface Entry control interface Control steel wool Ê¡˜Jšœ™Jšœ2™2J˜Jšœ˜Jšœb˜bJ˜šœÏkœ˜ J˜šœ!™!Jšœ œ˜Jšœ œ˜—J™šœ*™*Jšœ œ˜Jšœ œ˜Jšœœ˜ —J˜™ Jšœ1œ˜6Jšœ$œ˜)Jšœœ˜Jšœuœ˜zJšœœ˜Jšœlœœ˜‹Jšœœ˜Jšœ:œ˜@Jšœœ˜—J˜™Jšœœ˜Jšœ'˜'Jšœœ˜Jšœ*˜*—J˜™Jšœ!œ˜&—J™šœ™Jšœœ˜Jšœ<œ˜AJšœ'˜'Jšœ*˜*Jšœ œ˜Jšœœ˜Jšœœ˜Jšœœ˜Jšœœ˜Jšœœ˜Jšœœ˜Jšœ œ˜Jšœœ˜ Jšœ œ˜Jšœœ˜Jšœ œ˜—J˜™Jšœœ˜Jšœœ˜JšœPœ˜U—J™šœ™Jšœ(œ˜-Jšœ*œ˜/Jšœœ˜Jšœœ˜!Jšœ&œ˜+Jšœ(œ˜-Jšœ~œ˜ƒJšœ0˜5Jšœ˜—J˜™Jšœ‚œ˜‡Jšœ œ˜Jšœ8œ˜>Jšœœ˜%Jšœ8˜=—J˜J˜˜J˜™JšœRœ˜WJšœœ˜"Jšœœ˜—J˜™Jšœ¹œ˜¾—J™™Jšœ¦œ˜«—J˜™Jšœ}œ˜‚—J™™Jšœðœ˜õ—J˜™Jšœ,˜,Jšœœ˜Jšœœ˜Jšœ!œ˜'Jšœ œ˜—J˜J˜J˜J˜Jšœ˜Jšœ˜—Jš˜——…— Ô+