--CacheMCtl.Mesa
--created by RoseTranslate from CacheMCtl.Rose of May 22, 1984 8:24:17 pm PDT for Barth.pa at May 30, 1984 4:29:31 pm PDT


DIRECTORY
RoseTypes, RoseCreate, Dragon, SwitchTypes, NumTypes, Mnemonics, CacheMCtlSequencer, CacheMCtlEntryCtl, CacheMCtlFlagCtl, CacheMCtlRAMCtl, CacheMCtlCAMCtl;

CacheMCtl: CEDAR PROGRAM
IMPORTS RoseCreate, NumTypes, Mnemonics, CacheMCtlSequencer, CacheMCtlEntryCtl, CacheMCtlFlagCtl, CacheMCtlRAMCtl, CacheMCtlCAMCtl =

BEGIN OPEN
RoseTypes;

--Signal Type decls
PBusFaults: TYPE = Dragon.PBusFaults;
PBusCommands: TYPE = Dragon.PBusCommands;
MBusCommands: TYPE = Dragon.MBusCommands;


RegisterCells: PROC =
BEGIN
CreateMCtlPorts[];
[] _ RoseCreate.RegisterCellClass[className: "MCtl",
expandProc: MCtlExpand,
ioCreator: CreateMCtlIO, initializer: NIL,
evals: [],
blackBox: NIL, stateToo: NIL,
ports: MCtlPorts,
drivePrototype: NEW [MCtlDrive]];
END;

CreateMCtlPorts: PROC = {MCtlPorts _ RoseCreate.PortsFromFile["CacheMCtl.MCtl.rosePorts"]};

MCtlIORef: TYPE = REF MCtlIORec;
MCtlIORec: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0..32767],
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0..32767],
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0..32767],
LatchBias(2:15..15): BOOLEAN,
fill3(3:0..14): [0..32767],
PhAb(3:15..15): BOOLEAN,
fill4(4:0..14): [0..32767],
PhBb(4:15..15): BOOLEAN,
fill5(5:0..14): [0..32767],
PhAh(5:15..15): BOOLEAN,
fill6(6:0..14): [0..32767],
PhBh(6:15..15): BOOLEAN,
fill7(7:0..14): [0..32767],
Resetb(7:15..15): BOOLEAN,
fill8(8:0..14): [0..32767],
nVirtualMatch(8:15..15): BOOLEAN,
fill9(9:0..14): [0..32767],
nMatchPageClean(9:15..15): BOOLEAN,
fill10(10:0..14): [0..32767],
nMatchCellShared(10:15..15): BOOLEAN,
fill11(11:0..14): [0..32767],
nMapValid(11:15..15): BOOLEAN,
fill12(12:0..14): [0..32767],
nRealMatch(12:15..15): BOOLEAN,
fill13(13:0..14): [0..32767],
nVictimClean(13:15..15): BOOLEAN,
fill14(14:0..7): [0..255],
CellAdr(14:8..15): [0..255],
fill15(15:0..7): [0..255],
nCellAdr(15:8..15): [0..255],
fill16(16:0..14): [0..32767],
VirtualAccess(16:15..15): BOOLEAN,
fill17(17:0..14): [0..32767],
nVirtualAccess(17:15..15): BOOLEAN,
fill18(18:0..14): [0..32767],
SelCell(18:15..15): BOOLEAN,
fill19(19:0..14): [0..32767],
SelVictimAdr(19:15..15): BOOLEAN,
fill20(20:0..14): [0..32767],
SelMapAdr(20:15..15): BOOLEAN,
fill21(21:0..14): [0..32767],
SelRealData(21:15..15): BOOLEAN,
fill22(22:0..14): [0..32767],
SelPageFlag(22:15..15): BOOLEAN,
fill23(23:0..14): [0..32767],
SelVictimData(23:15..15): BOOLEAN,
fill24(24:0..14): [0..32767],
SelRealAdr(24:15..15): BOOLEAN,
fill25(25:0..14): [0..32767],
FinishSharedStore(25:15..15): BOOLEAN,
VPValid(26:0..15): SwitchTypes.SwitchVal,
nVPValid(27:0..15): SwitchTypes.SwitchVal,
RPValid(28:0..15): SwitchTypes.SwitchVal,
nRPValid(29:0..15): SwitchTypes.SwitchVal,
RPDirty(30:0..15): SwitchTypes.SwitchVal,
nRPDirty(31:0..15): SwitchTypes.SwitchVal,
Master(32:0..15): SwitchTypes.SwitchVal,
nMaster(33:0..15): SwitchTypes.SwitchVal,
Shared(34:0..15): SwitchTypes.SwitchVal,
nShared(35:0..15): SwitchTypes.SwitchVal,
Victim(36:0..15): SwitchTypes.SwitchVal,
nVictim(37:0..15): SwitchTypes.SwitchVal,
TIP(38:0..15): SwitchTypes.SwitchVal,
nTIP(39:0..15): SwitchTypes.SwitchVal,
Broken(40:0..15): SwitchTypes.SwitchVal,
nBroken(41:0..15): SwitchTypes.SwitchVal,
fill42(42:0..14): [0..32767],
MAdrLow(42:15..15): BOOLEAN,
fill43(43:0..14): [0..32767],
nMAdrLow(43:15..15): BOOLEAN,
fill44(44:0..14): [0..32767],
VictimFeedback(44:15..15): BOOLEAN,
fill45(45:0..14): [0..32767],
nVictimFeedback(45:15..15): BOOLEAN,
fill46(46:0..14): [0..32767],
ShiftVictim(46:15..15): BOOLEAN,
fill47(47:0..14): [0..32767],
nShiftVictim(47:15..15): BOOLEAN,
fill48(48:0..14): [0..32767],
ForceDataSelect(48:15..15): BOOLEAN,
fill49(49:0..14): [0..32767],
MDoneAB(49:15..15): BOOLEAN,
fill50(50:0..14): [0..32767],
MHeldAB(50:15..15): BOOLEAN,
fill51(51:0..12): [0..8191],
MFaultAB(51:13..15): PBusFaults,
fill52(52:0..14): [0..32767],
PKillRequestB(52:15..15): BOOLEAN,
fill53(53:0..14): [0..32767],
PAdrHigh(53:15..15): BOOLEAN,
fill54(54:0..14): [0..32767],
PAdrLowToM(54:15..15): BOOLEAN,
fill55(55:0..11): [0..4095],
PCmdToMAB(55:12..15): PBusCommands,
fill56(56:0..14): [0..32767],
DoShiftBA(56:15..15): BOOLEAN,
fill57(57:0..14): [0..32767],
DoExecuteBA(57:15..15): BOOLEAN,
fill58(58:0..14): [0..32767],
DoHoldBA(58:15..15): BOOLEAN,
MDataI(59:0..31): ARRAY [0..2) OF CARDINAL,
fill60(61:0..14): [0..32767],
MDataDrive(61:15..15): BOOLEAN,
fill61(62:0..14): [0..32767],
MDataIDrive(62:15..15): BOOLEAN,
fill62(63:0..14): [0..32767],
MDataPipeBypass(63:15..15): BOOLEAN,
fill63(64:0..14): [0..32767],
MDataPipeTransfer(64:15..15): BOOLEAN,
fill64(65:0..11): [0..4095],
MCmdIn(65:12..15): MBusCommands,
fill65(66:0..11): [0..4095],
MCmdOutBA(66:12..15): MBusCommands,
fill66(67:0..14): [0..32767],
MCmdDrive(67:15..15): BOOLEAN,
fill67(68:0..14): [0..32767],
MCmdDriveToDataTransport(68:15..15): BOOLEAN,
fill68(69:0..14): [0..32767],
MCmdDriveToNoOp(69:15..15): BOOLEAN,
fill69(70:0..14): [0..32767],
MNSharedSenseBA(70:15..15): BOOLEAN,
fill70(71:0..14): [0..32767],
MNSharedDriveHigh(71:15..15): BOOLEAN,
fill71(72:0..14): [0..32767],
MNSharedDriveLow(72:15..15): BOOLEAN,
fill72(73:0..14): [0..32767],
MNErrorDriveLow(73:15..15): BOOLEAN,
fill73(74:0..14): [0..32767],
MReadySense(74:15..15): BOOLEAN,
fill74(75:0..14): [0..32767],
MRqIBA(75:15..15): BOOLEAN,
fill75(76:0..14): [0..32767],
MNewRqIBA(76:15..15): BOOLEAN,
fill76(77:0..14): [0..32767],
MNewRqEnableBA(77:15..15): BOOLEAN,
fill77(78:0..14): [0..32767],
MGntSense(78:15..15): BOOLEAN,
fill78(79:0..14): [0..32767],
ShiftDataToMCtl(79:15..15): BOOLEAN,
fill79(80:0..14): [0..32767],
ShiftDataToMCAM(80:15..15): BOOLEAN,
fill80(81:0..14): [0..32767],
ShiftEqual(81:15..15): BOOLEAN,
fill81(82:0..14): [0..32767],
nShiftEqual(82:15..15): BOOLEAN,
fill82(83:0..14): [0..32767],
ShiftFeedBack(83:15..15): BOOLEAN,
fill83(84:0..14): [0..32767],
nShiftFeedBack(84:15..15): BOOLEAN,
fill84(85:0..14): [0..32767],
ShiftShift(85:15..15): BOOLEAN,
fill85(86:0..14): [0..32767],
nShiftShift(86:15..15): BOOLEAN,
fill86(87:0..14): [0..32767],
PageAccessToAccess(87:15..15): BOOLEAN,
fill87(88:0..14): [0..32767],
BlockAccessToAccess(88:15..15): BOOLEAN,
fill88(89:0..14): [0..32767],
PageVirtualToAccess(89:15..15): BOOLEAN,
fill89(90:0..14): [0..32767],
BlockVirtualToAccess(90:15..15): BOOLEAN,
fill90(91:0..14): [0..32767],
MatchToAccess(91:15..15): BOOLEAN,
fill91(92:0..14): [0..32767],
MDataToMatch(92:15..15): BOOLEAN,
fill92(93:0..14): [0..32767],
AccessToMatch(93:15..15): BOOLEAN,
fill93(94:0..14): [0..32767],
PageAccessToMData(94:15..15): BOOLEAN,
fill94(95:0..14): [0..32767],
nPageAccessToMData(95:15..15): BOOLEAN,
fill95(96:0..14): [0..32767],
BlockAccessToMData(96:15..15): BOOLEAN,
fill96(97:0..14): [0..32767],
nBlockAccessToMData(97:15..15): BOOLEAN,
fill97(98:0..14): [0..32767],
AccessToPageBlockAccess(98:15..15): BOOLEAN,
fill98(99:0..14): [0..32767],
nAccessToPageBlockAccess(99:15..15): BOOLEAN,
fill99(100:0..14): [0..32767],
ShiftToPageBlockAccess(100:15..15): BOOLEAN,
fill100(101:0..14): [0..32767],
nShiftToPageBlockAccess(101:15..15): BOOLEAN,
fill101(102:0..14): [0..32767],
AccessDrive(102:15..15): BOOLEAN,
fill102(103:0..14): [0..32767],
nAccessDrive(103:15..15): BOOLEAN,
fill103(104:0..14): [0..32767],
PageBlockAccessToShift(104:15..15): BOOLEAN,
fill104(105:0..14): [0..32767],
nPageBlockAccessToShift(105:15..15): BOOLEAN,
fill105(106:0..14): [0..32767],
nCAMAccessPrecharge(106:15..15): BOOLEAN,
fill106(107:0..14): [0..32767],
nMBitsPrecharge(107:15..15): BOOLEAN,
fill107(108:0..14): [0..32767],
MuxRight(108:15..15): BOOLEAN,
fill108(109:0..14): [0..32767],
MuxLeft(109:15..15): BOOLEAN,
fill109(110:0..14): [0..32767],
MBitsDrive(110:15..15): BOOLEAN,
fill110(111:0..14): [0..32767],
nMBitsDrive(111:15..15): BOOLEAN,
fill111(112:0..14): [0..32767],
MRamRegToMDataI(112:15..15): BOOLEAN,
fill112(113:0..14): [0..32767],
nMRamRegToMDataI(113:15..15): BOOLEAN,
fill113(114:0..14): [0..32767],
SenseMBits(114:15..15): BOOLEAN,
fill114(115:0..14): [0..32767],
SenseMDataI(115:15..15): BOOLEAN,
fill115(116:0..14): [0..32767],
ParityIn(116:15..15): BOOLEAN,
fill116(117:0..14): [0..32767],
ParityOut(117:15..15): BOOLEAN,
fill117(118:0..14): [0..32767],
SensePBitsLeft(118:15..15): BOOLEAN,
fill118(119:0..14): [0..32767],
SensePBitsRight(119:15..15): BOOLEAN,
fill119(120:0..14): [0..32767],
DrivePBits(120:15..15): BOOLEAN,
fill120(121:0..14): [0..32767],
nDrivePBits(121:15..15): BOOLEAN,
fill121(122:0..14): [0..32767],
MRamRegToMBits(122:15..15): BOOLEAN,
fill122(123:0..14): [0..32767],
nMRamRegToMBits(123:15..15): BOOLEAN,
fill123(124:0..14): [0..32767],
ShiftToMBits(124:15..15): BOOLEAN,
fill124(125:0..14): [0..32767],
nShiftToMBits(125:15..15): BOOLEAN,
fill125(126:0..14): [0..32767],
MBitsToShift(126:15..15): BOOLEAN,
fill126(127:0..14): [0..32767],
nMBitsToShift(127:15..15): BOOLEAN];

-- port indices:
MCtlVPValidPortIndex: CARDINAL = 26;
MCtlNVPValidPortIndex: CARDINAL = 27;
MCtlRPValidPortIndex: CARDINAL = 28;
MCtlNRPValidPortIndex: CARDINAL = 29;
MCtlRPDirtyPortIndex: CARDINAL = 30;
MCtlNRPDirtyPortIndex: CARDINAL = 31;
MCtlMasterPortIndex: CARDINAL = 32;
MCtlNMasterPortIndex: CARDINAL = 33;
MCtlSharedPortIndex: CARDINAL = 34;
MCtlNSharedPortIndex: CARDINAL = 35;
MCtlVictimPortIndex: CARDINAL = 36;
MCtlNVictimPortIndex: CARDINAL = 37;
MCtlTIPPortIndex: CARDINAL = 38;
MCtlNTIPPortIndex: CARDINAL = 39;
MCtlBrokenPortIndex: CARDINAL = 40;
MCtlNBrokenPortIndex: CARDINAL = 41;

MCtlDrive: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0 .. 32768),
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0 .. 32768),
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0 .. 32768),
LatchBias(2:15..15): BOOLEAN,
fill3(3:0..14): [0 .. 32768),
PhAb(3:15..15): BOOLEAN,
fill4(4:0..14): [0 .. 32768),
PhBb(4:15..15): BOOLEAN,
fill5(5:0..14): [0 .. 32768),
PhAh(5:15..15): BOOLEAN,
fill6(6:0..14): [0 .. 32768),
PhBh(6:15..15): BOOLEAN,
fill7(7:0..14): [0 .. 32768),
Resetb(7:15..15): BOOLEAN,
fill8(8:0..14): [0 .. 32768),
nVirtualMatch(8:15..15): BOOLEAN,
fill9(9:0..14): [0 .. 32768),
nMatchPageClean(9:15..15): BOOLEAN,
fill10(10:0..14): [0 .. 32768),
nMatchCellShared(10:15..15): BOOLEAN,
fill11(11:0..14): [0 .. 32768),
nMapValid(11:15..15): BOOLEAN,
fill12(12:0..14): [0 .. 32768),
nRealMatch(12:15..15): BOOLEAN,
fill13(13:0..14): [0 .. 32768),
nVictimClean(13:15..15): BOOLEAN,
fill14(14:0..14): [0 .. 32768),
CellAdr(14:15..15): BOOLEAN,
fill15(15:0..14): [0 .. 32768),
nCellAdr(15:15..15): BOOLEAN,
fill16(16:0..14): [0 .. 32768),
VirtualAccess(16:15..15): BOOLEAN,
fill17(17:0..14): [0 .. 32768),
nVirtualAccess(17:15..15): BOOLEAN,
fill18(18:0..14): [0 .. 32768),
SelCell(18:15..15): BOOLEAN,
fill19(19:0..14): [0 .. 32768),
SelVictimAdr(19:15..15): BOOLEAN,
fill20(20:0..14): [0 .. 32768),
SelMapAdr(20:15..15): BOOLEAN,
fill21(21:0..14): [0 .. 32768),
SelRealData(21:15..15): BOOLEAN,
fill22(22:0..14): [0 .. 32768),
SelPageFlag(22:15..15): BOOLEAN,
fill23(23:0..14): [0 .. 32768),
SelVictimData(23:15..15): BOOLEAN,
fill24(24:0..14): [0 .. 32768),
SelRealAdr(24:15..15): BOOLEAN,
fill25(25:0..14): [0 .. 32768),
FinishSharedStore(25:15..15): BOOLEAN,
fill26(26:0..14): [0 .. 32768),
VPValid(26:15..15): BOOLEAN,
fill27(27:0..14): [0 .. 32768),
nVPValid(27:15..15): BOOLEAN,
fill28(28:0..14): [0 .. 32768),
RPValid(28:15..15): BOOLEAN,
fill29(29:0..14): [0 .. 32768),
nRPValid(29:15..15): BOOLEAN,
fill30(30:0..14): [0 .. 32768),
RPDirty(30:15..15): BOOLEAN,
fill31(31:0..14): [0 .. 32768),
nRPDirty(31:15..15): BOOLEAN,
fill32(32:0..14): [0 .. 32768),
Master(32:15..15): BOOLEAN,
fill33(33:0..14): [0 .. 32768),
nMaster(33:15..15): BOOLEAN,
fill34(34:0..14): [0 .. 32768),
Shared(34:15..15): BOOLEAN,
fill35(35:0..14): [0 .. 32768),
nShared(35:15..15): BOOLEAN,
fill36(36:0..14): [0 .. 32768),
Victim(36:15..15): BOOLEAN,
fill37(37:0..14): [0 .. 32768),
nVictim(37:15..15): BOOLEAN,
fill38(38:0..14): [0 .. 32768),
TIP(38:15..15): BOOLEAN,
fill39(39:0..14): [0 .. 32768),
nTIP(39:15..15): BOOLEAN,
fill40(40:0..14): [0 .. 32768),
Broken(40:15..15): BOOLEAN,
fill41(41:0..14): [0 .. 32768),
nBroken(41:15..15): BOOLEAN,
fill42(42:0..14): [0 .. 32768),
MAdrLow(42:15..15): BOOLEAN,
fill43(43:0..14): [0 .. 32768),
nMAdrLow(43:15..15): BOOLEAN,
fill44(44:0..14): [0 .. 32768),
VictimFeedback(44:15..15): BOOLEAN,
fill45(45:0..14): [0 .. 32768),
nVictimFeedback(45:15..15): BOOLEAN,
fill46(46:0..14): [0 .. 32768),
ShiftVictim(46:15..15): BOOLEAN,
fill47(47:0..14): [0 .. 32768),
nShiftVictim(47:15..15): BOOLEAN,
fill48(48:0..14): [0 .. 32768),
ForceDataSelect(48:15..15): BOOLEAN,
fill49(49:0..14): [0 .. 32768),
MDoneAB(49:15..15): BOOLEAN,
fill50(50:0..14): [0 .. 32768),
MHeldAB(50:15..15): BOOLEAN,
fill51(51:0..14): [0 .. 32768),
MFaultAB(51:15..15): BOOLEAN,
fill52(52:0..14): [0 .. 32768),
PKillRequestB(52:15..15): BOOLEAN,
fill53(53:0..14): [0 .. 32768),
PAdrHigh(53:15..15): BOOLEAN,
fill54(54:0..14): [0 .. 32768),
PAdrLowToM(54:15..15): BOOLEAN,
fill55(55:0..14): [0 .. 32768),
PCmdToMAB(55:15..15): BOOLEAN,
fill56(56:0..14): [0 .. 32768),
DoShiftBA(56:15..15): BOOLEAN,
fill57(57:0..14): [0 .. 32768),
DoExecuteBA(57:15..15): BOOLEAN,
fill58(58:0..14): [0 .. 32768),
DoHoldBA(58:15..15): BOOLEAN,
fill59(59:0..14): [0 .. 32768),
MDataI(59:15..15): BOOLEAN,
fill60(60:0..14): [0 .. 32768),
MDataDrive(60:15..15): BOOLEAN,
fill61(61:0..14): [0 .. 32768),
MDataIDrive(61:15..15): BOOLEAN,
fill62(62:0..14): [0 .. 32768),
MDataPipeBypass(62:15..15): BOOLEAN,
fill63(63:0..14): [0 .. 32768),
MDataPipeTransfer(63:15..15): BOOLEAN,
fill64(64:0..14): [0 .. 32768),
MCmdIn(64:15..15): BOOLEAN,
fill65(65:0..14): [0 .. 32768),
MCmdOutBA(65:15..15): BOOLEAN,
fill66(66:0..14): [0 .. 32768),
MCmdDrive(66:15..15): BOOLEAN,
fill67(67:0..14): [0 .. 32768),
MCmdDriveToDataTransport(67:15..15): BOOLEAN,
fill68(68:0..14): [0 .. 32768),
MCmdDriveToNoOp(68:15..15): BOOLEAN,
fill69(69:0..14): [0 .. 32768),
MNSharedSenseBA(69:15..15): BOOLEAN,
fill70(70:0..14): [0 .. 32768),
MNSharedDriveHigh(70:15..15): BOOLEAN,
fill71(71:0..14): [0 .. 32768),
MNSharedDriveLow(71:15..15): BOOLEAN,
fill72(72:0..14): [0 .. 32768),
MNErrorDriveLow(72:15..15): BOOLEAN,
fill73(73:0..14): [0 .. 32768),
MReadySense(73:15..15): BOOLEAN,
fill74(74:0..14): [0 .. 32768),
MRqIBA(74:15..15): BOOLEAN,
fill75(75:0..14): [0 .. 32768),
MNewRqIBA(75:15..15): BOOLEAN,
fill76(76:0..14): [0 .. 32768),
MNewRqEnableBA(76:15..15): BOOLEAN,
fill77(77:0..14): [0 .. 32768),
MGntSense(77:15..15): BOOLEAN,
fill78(78:0..14): [0 .. 32768),
ShiftDataToMCtl(78:15..15): BOOLEAN,
fill79(79:0..14): [0 .. 32768),
ShiftDataToMCAM(79:15..15): BOOLEAN,
fill80(80:0..14): [0 .. 32768),
ShiftEqual(80:15..15): BOOLEAN,
fill81(81:0..14): [0 .. 32768),
nShiftEqual(81:15..15): BOOLEAN,
fill82(82:0..14): [0 .. 32768),
ShiftFeedBack(82:15..15): BOOLEAN,
fill83(83:0..14): [0 .. 32768),
nShiftFeedBack(83:15..15): BOOLEAN,
fill84(84:0..14): [0 .. 32768),
ShiftShift(84:15..15): BOOLEAN,
fill85(85:0..14): [0 .. 32768),
nShiftShift(85:15..15): BOOLEAN,
fill86(86:0..14): [0 .. 32768),
PageAccessToAccess(86:15..15): BOOLEAN,
fill87(87:0..14): [0 .. 32768),
BlockAccessToAccess(87:15..15): BOOLEAN,
fill88(88:0..14): [0 .. 32768),
PageVirtualToAccess(88:15..15): BOOLEAN,
fill89(89:0..14): [0 .. 32768),
BlockVirtualToAccess(89:15..15): BOOLEAN,
fill90(90:0..14): [0 .. 32768),
MatchToAccess(90:15..15): BOOLEAN,
fill91(91:0..14): [0 .. 32768),
MDataToMatch(91:15..15): BOOLEAN,
fill92(92:0..14): [0 .. 32768),
AccessToMatch(92:15..15): BOOLEAN,
fill93(93:0..14): [0 .. 32768),
PageAccessToMData(93:15..15): BOOLEAN,
fill94(94:0..14): [0 .. 32768),
nPageAccessToMData(94:15..15): BOOLEAN,
fill95(95:0..14): [0 .. 32768),
BlockAccessToMData(95:15..15): BOOLEAN,
fill96(96:0..14): [0 .. 32768),
nBlockAccessToMData(96:15..15): BOOLEAN,
fill97(97:0..14): [0 .. 32768),
AccessToPageBlockAccess(97:15..15): BOOLEAN,
fill98(98:0..14): [0 .. 32768),
nAccessToPageBlockAccess(98:15..15): BOOLEAN,
fill99(99:0..14): [0 .. 32768),
ShiftToPageBlockAccess(99:15..15): BOOLEAN,
fill100(100:0..14): [0 .. 32768),
nShiftToPageBlockAccess(100:15..15): BOOLEAN,
fill101(101:0..14): [0 .. 32768),
AccessDrive(101:15..15): BOOLEAN,
fill102(102:0..14): [0 .. 32768),
nAccessDrive(102:15..15): BOOLEAN,
fill103(103:0..14): [0 .. 32768),
PageBlockAccessToShift(103:15..15): BOOLEAN,
fill104(104:0..14): [0 .. 32768),
nPageBlockAccessToShift(104:15..15): BOOLEAN,
fill105(105:0..14): [0 .. 32768),
nCAMAccessPrecharge(105:15..15): BOOLEAN,
fill106(106:0..14): [0 .. 32768),
nMBitsPrecharge(106:15..15): BOOLEAN,
fill107(107:0..14): [0 .. 32768),
MuxRight(107:15..15): BOOLEAN,
fill108(108:0..14): [0 .. 32768),
MuxLeft(108:15..15): BOOLEAN,
fill109(109:0..14): [0 .. 32768),
MBitsDrive(109:15..15): BOOLEAN,
fill110(110:0..14): [0 .. 32768),
nMBitsDrive(110:15..15): BOOLEAN,
fill111(111:0..14): [0 .. 32768),
MRamRegToMDataI(111:15..15): BOOLEAN,
fill112(112:0..14): [0 .. 32768),
nMRamRegToMDataI(112:15..15): BOOLEAN,
fill113(113:0..14): [0 .. 32768),
SenseMBits(113:15..15): BOOLEAN,
fill114(114:0..14): [0 .. 32768),
SenseMDataI(114:15..15): BOOLEAN,
fill115(115:0..14): [0 .. 32768),
ParityIn(115:15..15): BOOLEAN,
fill116(116:0..14): [0 .. 32768),
ParityOut(116:15..15): BOOLEAN,
fill117(117:0..14): [0 .. 32768),
SensePBitsLeft(117:15..15): BOOLEAN,
fill118(118:0..14): [0 .. 32768),
SensePBitsRight(118:15..15): BOOLEAN,
fill119(119:0..14): [0 .. 32768),
DrivePBits(119:15..15): BOOLEAN,
fill120(120:0..14): [0 .. 32768),
nDrivePBits(120:15..15): BOOLEAN,
fill121(121:0..14): [0 .. 32768),
MRamRegToMBits(121:15..15): BOOLEAN,
fill122(122:0..14): [0 .. 32768),
nMRamRegToMBits(122:15..15): BOOLEAN,
fill123(123:0..14): [0 .. 32768),
ShiftToMBits(123:15..15): BOOLEAN,
fill124(124:0..14): [0 .. 32768),
nShiftToMBits(124:15..15): BOOLEAN,
fill125(125:0..14): [0 .. 32768),
MBitsToShift(125:15..15): BOOLEAN,
fill126(126:0..14): [0 .. 32768),
nMBitsToShift(126:15..15): BOOLEAN];


MCtlExpand: ExpandProc = {
PrivateLookupNode: PROC [name: ROPE] RETURNS [node: Node] = {node _ RoseCreate.LookupNode[from: thisCell, path: LIST[name]]};
Vdd: Node _ PrivateLookupNode["Vdd"];
Gnd: Node _ PrivateLookupNode["Gnd"];
LatchBias: Node _ PrivateLookupNode["LatchBias"];
PhAb: Node _ PrivateLookupNode["PhAb"];
PhBb: Node _ PrivateLookupNode["PhBb"];
PhAh: Node _ PrivateLookupNode["PhAh"];
PhBh: Node _ PrivateLookupNode["PhBh"];
Resetb: Node _ PrivateLookupNode["Resetb"];
nVirtualMatch: Node _ PrivateLookupNode["nVirtualMatch"];
nMatchPageClean: Node _ PrivateLookupNode["nMatchPageClean"];
nMatchCellShared: Node _ PrivateLookupNode["nMatchCellShared"];
nMapValid: Node _ PrivateLookupNode["nMapValid"];
nRealMatch: Node _ PrivateLookupNode["nRealMatch"];
nVictimClean: Node _ PrivateLookupNode["nVictimClean"];
CellAdr: Node _ PrivateLookupNode["CellAdr"];
nCellAdr: Node _ PrivateLookupNode["nCellAdr"];
VirtualAccess: Node _ PrivateLookupNode["VirtualAccess"];
nVirtualAccess: Node _ PrivateLookupNode["nVirtualAccess"];
SelCell: Node _ PrivateLookupNode["SelCell"];
SelVictimAdr: Node _ PrivateLookupNode["SelVictimAdr"];
SelMapAdr: Node _ PrivateLookupNode["SelMapAdr"];
SelRealData: Node _ PrivateLookupNode["SelRealData"];
SelPageFlag: Node _ PrivateLookupNode["SelPageFlag"];
SelVictimData: Node _ PrivateLookupNode["SelVictimData"];
SelRealAdr: Node _ PrivateLookupNode["SelRealAdr"];
FinishSharedStore: Node _ PrivateLookupNode["FinishSharedStore"];
VPValid: Node _ PrivateLookupNode["VPValid"];
nVPValid: Node _ PrivateLookupNode["nVPValid"];
RPValid: Node _ PrivateLookupNode["RPValid"];
nRPValid: Node _ PrivateLookupNode["nRPValid"];
RPDirty: Node _ PrivateLookupNode["RPDirty"];
nRPDirty: Node _ PrivateLookupNode["nRPDirty"];
Master: Node _ PrivateLookupNode["Master"];
nMaster: Node _ PrivateLookupNode["nMaster"];
Shared: Node _ PrivateLookupNode["Shared"];
nShared: Node _ PrivateLookupNode["nShared"];
Victim: Node _ PrivateLookupNode["Victim"];
nVictim: Node _ PrivateLookupNode["nVictim"];
TIP: Node _ PrivateLookupNode["TIP"];
nTIP: Node _ PrivateLookupNode["nTIP"];
Broken: Node _ PrivateLookupNode["Broken"];
nBroken: Node _ PrivateLookupNode["nBroken"];
MAdrLow: Node _ PrivateLookupNode["MAdrLow"];
nMAdrLow: Node _ PrivateLookupNode["nMAdrLow"];
VictimFeedback: Node _ PrivateLookupNode["VictimFeedback"];
nVictimFeedback: Node _ PrivateLookupNode["nVictimFeedback"];
ShiftVictim: Node _ PrivateLookupNode["ShiftVictim"];
nShiftVictim: Node _ PrivateLookupNode["nShiftVictim"];
ForceDataSelect: Node _ PrivateLookupNode["ForceDataSelect"];
MDoneAB: Node _ PrivateLookupNode["MDoneAB"];
MHeldAB: Node _ PrivateLookupNode["MHeldAB"];
MFaultAB: Node _ PrivateLookupNode["MFaultAB"];
PKillRequestB: Node _ PrivateLookupNode["PKillRequestB"];
PAdrHigh: Node _ PrivateLookupNode["PAdrHigh"];
PAdrLowToM: Node _ PrivateLookupNode["PAdrLowToM"];
PCmdToMAB: Node _ PrivateLookupNode["PCmdToMAB"];
DoShiftBA: Node _ PrivateLookupNode["DoShiftBA"];
DoExecuteBA: Node _ PrivateLookupNode["DoExecuteBA"];
DoHoldBA: Node _ PrivateLookupNode["DoHoldBA"];
MDataI: Node _ PrivateLookupNode["MDataI"];
MDataDrive: Node _ PrivateLookupNode["MDataDrive"];
MDataIDrive: Node _ PrivateLookupNode["MDataIDrive"];
MDataPipeBypass: Node _ PrivateLookupNode["MDataPipeBypass"];
MDataPipeTransfer: Node _ PrivateLookupNode["MDataPipeTransfer"];
MCmdIn: Node _ PrivateLookupNode["MCmdIn"];
MCmdOutBA: Node _ PrivateLookupNode["MCmdOutBA"];
MCmdDrive: Node _ PrivateLookupNode["MCmdDrive"];
MCmdDriveToDataTransport: Node _ PrivateLookupNode["MCmdDriveToDataTransport"];
MCmdDriveToNoOp: Node _ PrivateLookupNode["MCmdDriveToNoOp"];
MNSharedSenseBA: Node _ PrivateLookupNode["MNSharedSenseBA"];
MNSharedDriveHigh: Node _ PrivateLookupNode["MNSharedDriveHigh"];
MNSharedDriveLow: Node _ PrivateLookupNode["MNSharedDriveLow"];
MNErrorDriveLow: Node _ PrivateLookupNode["MNErrorDriveLow"];
MReadySense: Node _ PrivateLookupNode["MReadySense"];
MRqIBA: Node _ PrivateLookupNode["MRqIBA"];
MNewRqIBA: Node _ PrivateLookupNode["MNewRqIBA"];
MNewRqEnableBA: Node _ PrivateLookupNode["MNewRqEnableBA"];
MGntSense: Node _ PrivateLookupNode["MGntSense"];
ShiftDataToMCtl: Node _ PrivateLookupNode["ShiftDataToMCtl"];
ShiftDataToMCAM: Node _ PrivateLookupNode["ShiftDataToMCAM"];
ShiftEqual: Node _ PrivateLookupNode["ShiftEqual"];
nShiftEqual: Node _ PrivateLookupNode["nShiftEqual"];
ShiftFeedBack: Node _ PrivateLookupNode["ShiftFeedBack"];
nShiftFeedBack: Node _ PrivateLookupNode["nShiftFeedBack"];
ShiftShift: Node _ PrivateLookupNode["ShiftShift"];
nShiftShift: Node _ PrivateLookupNode["nShiftShift"];
PageAccessToAccess: Node _ PrivateLookupNode["PageAccessToAccess"];
BlockAccessToAccess: Node _ PrivateLookupNode["BlockAccessToAccess"];
PageVirtualToAccess: Node _ PrivateLookupNode["PageVirtualToAccess"];
BlockVirtualToAccess: Node _ PrivateLookupNode["BlockVirtualToAccess"];
MatchToAccess: Node _ PrivateLookupNode["MatchToAccess"];
MDataToMatch: Node _ PrivateLookupNode["MDataToMatch"];
AccessToMatch: Node _ PrivateLookupNode["AccessToMatch"];
PageAccessToMData: Node _ PrivateLookupNode["PageAccessToMData"];
nPageAccessToMData: Node _ PrivateLookupNode["nPageAccessToMData"];
BlockAccessToMData: Node _ PrivateLookupNode["BlockAccessToMData"];
nBlockAccessToMData: Node _ PrivateLookupNode["nBlockAccessToMData"];
AccessToPageBlockAccess: Node _ PrivateLookupNode["AccessToPageBlockAccess"];
nAccessToPageBlockAccess: Node _ PrivateLookupNode["nAccessToPageBlockAccess"];
ShiftToPageBlockAccess: Node _ PrivateLookupNode["ShiftToPageBlockAccess"];
nShiftToPageBlockAccess: Node _ PrivateLookupNode["nShiftToPageBlockAccess"];
AccessDrive: Node _ PrivateLookupNode["AccessDrive"];
nAccessDrive: Node _ PrivateLookupNode["nAccessDrive"];
PageBlockAccessToShift: Node _ PrivateLookupNode["PageBlockAccessToShift"];
nPageBlockAccessToShift: Node _ PrivateLookupNode["nPageBlockAccessToShift"];
nCAMAccessPrecharge: Node _ PrivateLookupNode["nCAMAccessPrecharge"];
nMBitsPrecharge: Node _ PrivateLookupNode["nMBitsPrecharge"];
MuxRight: Node _ PrivateLookupNode["MuxRight"];
MuxLeft: Node _ PrivateLookupNode["MuxLeft"];
MBitsDrive: Node _ PrivateLookupNode["MBitsDrive"];
nMBitsDrive: Node _ PrivateLookupNode["nMBitsDrive"];
MRamRegToMDataI: Node _ PrivateLookupNode["MRamRegToMDataI"];
nMRamRegToMDataI: Node _ PrivateLookupNode["nMRamRegToMDataI"];
SenseMBits: Node _ PrivateLookupNode["SenseMBits"];
SenseMDataI: Node _ PrivateLookupNode["SenseMDataI"];
ParityIn: Node _ PrivateLookupNode["ParityIn"];
ParityOut: Node _ PrivateLookupNode["ParityOut"];
SensePBitsLeft: Node _ PrivateLookupNode["SensePBitsLeft"];
SensePBitsRight: Node _ PrivateLookupNode["SensePBitsRight"];
DrivePBits: Node _ PrivateLookupNode["DrivePBits"];
nDrivePBits: Node _ PrivateLookupNode["nDrivePBits"];
MRamRegToMBits: Node _ PrivateLookupNode["MRamRegToMBits"];
nMRamRegToMBits: Node _ PrivateLookupNode["nMRamRegToMBits"];
ShiftToMBits: Node _ PrivateLookupNode["ShiftToMBits"];
nShiftToMBits: Node _ PrivateLookupNode["nShiftToMBits"];
MBitsToShift: Node _ PrivateLookupNode["MBitsToShift"];
nMBitsToShift: Node _ PrivateLookupNode["nMBitsToShift"];
NodeCreateHack1: PROC [name: ROPE] RETURNS [node: Node] = {node _ RoseCreate.CreateNode[within: thisCell, name: name, type: NumTypes.boolType]};
ShiftDataToFlagCtl: Node _ NodeCreateHack1["ShiftDataToFlagCtl"];
ShiftDataToSequencer: Node _ NodeCreateHack1["ShiftDataToSequencer"];
ShiftDataToEntryCtl: Node _ NodeCreateHack1["ShiftDataToEntryCtl"];
ShiftDataToCAMCtl: Node _ NodeCreateHack1["ShiftDataToCAMCtl"];
ShiftExecute: Node _ NodeCreateHack1["ShiftExecute"];
nShiftExecute: Node _ NodeCreateHack1["nShiftExecute"];
ReadEntry: Node _ NodeCreateHack1["ReadEntry"];
WriteEntry: Node _ NodeCreateHack1["WriteEntry"];
CAMMDataIToMatchReg: Node _ NodeCreateHack1["CAMMDataIToMatchReg"];
CAMGetAdrRefresh: Node _ NodeCreateHack1["CAMGetAdrRefresh"];
CAMGetAddress: Node _ NodeCreateHack1["CAMGetAddress"];
CAMPageAccessToMDataI: Node _ NodeCreateHack1["CAMPageAccessToMDataI"];
CAMLowBitsAccessToMDataI: Node _ NodeCreateHack1["CAMLowBitsAccessToMDataI"];
CAMAccessToMatch: Node _ NodeCreateHack1["CAMAccessToMatch"];
CAMMatchToAccess: Node _ NodeCreateHack1["CAMMatchToAccess"];
CAMVirtualAddressToAccess: Node _ NodeCreateHack1["CAMVirtualAddressToAccess"];
CAMDriveCAMAccess: Node _ NodeCreateHack1["CAMDriveCAMAccess"];
RAMMDataIToMRAMReg: Node _ NodeCreateHack1["RAMMDataIToMRAMReg"];
RAMMBitsToMRAMReg: Node _ NodeCreateHack1["RAMMBitsToMRAMReg"];
RAMMRAMRegToMDataI: Node _ NodeCreateHack1["RAMMRAMRegToMDataI"];
RAMMRAMRegToMBits: Node _ NodeCreateHack1["RAMMRAMRegToMBits"];
RAMMRAMRegToMBitsNoOrphan: Node _ NodeCreateHack1["RAMMRAMRegToMBitsNoOrphan"];
RAMPBitsToMRAMReg: Node _ NodeCreateHack1["RAMPBitsToMRAMReg"];
RAMLeftPBitsToMRAMReg: Node _ NodeCreateHack1["RAMLeftPBitsToMRAMReg"];
RAMMRAMRegToPBits: Node _ NodeCreateHack1["RAMMRAMRegToPBits"];
FlagSetShared: Node _ NodeCreateHack1["FlagSetShared"];
FlagRPDirtyVPValid: Node _ NodeCreateHack1["FlagRPDirtyVPValid"];
FlagFlagLatch: Node _ NodeCreateHack1["FlagFlagLatch"];
FlagResetVPValid: Node _ NodeCreateHack1["FlagResetVPValid"];
FlagSetFlags: Node _ NodeCreateHack1["FlagSetFlags"];
FlagSetTIP: Node _ NodeCreateHack1["FlagSetTIP"];
FlagResetTIP: Node _ NodeCreateHack1["FlagResetTIP"];
EntryMDataIToMAdrCtr: Node _ NodeCreateHack1["EntryMDataIToMAdrCtr"];
EntryGetAddress: Node _ NodeCreateHack1["EntryGetAddress"];
EntryGetAdrRefresh: Node _ NodeCreateHack1["EntryGetAdrRefresh"];
EntryRefresh: Node _ NodeCreateHack1["EntryRefresh"];
EntryMAdrCtrToMAdr: Node _ NodeCreateHack1["EntryMAdrCtrToMAdr"];
EntryIncMAdrCtr: Node _ NodeCreateHack1["EntryIncMAdrCtr"];
EntryZeroMAdrCtr: Node _ NodeCreateHack1["EntryZeroMAdrCtr"];
EntryPAdrToMAdrCtr: Node _ NodeCreateHack1["EntryPAdrToMAdrCtr"];
EntryLowBitsAccessToMDataI: Node _ NodeCreateHack1["EntryLowBitsAccessToMDataI"];
EntryLowBitsZeroToMDataI: Node _ NodeCreateHack1["EntryLowBitsZeroToMDataI"];
EntrySelRealData: Node _ NodeCreateHack1["EntrySelRealData"];
EntrySelPageFlag: Node _ NodeCreateHack1["EntrySelPageFlag"];
EntrySelVictimData: Node _ NodeCreateHack1["EntrySelVictimData"];
EntrySelectVictimOrOrphan: Node _ NodeCreateHack1["EntrySelectVictimOrOrphan"];
EntryVirtualAccess: Node _ NodeCreateHack1["EntryVirtualAccess"];
EntrynVirtualAccess: Node _ NodeCreateHack1["EntrynVirtualAccess"];
EntryShiftVictim: Node _ NodeCreateHack1["EntryShiftVictim"];
EntryFinishSharedStore: Node _ NodeCreateHack1["EntryFinishSharedStore"];
GetAdrCmdBA: Node _ RoseCreate.CreateNode[within: thisCell, name: "GetAdrCmdBA", type: Mnemonics.Mnemonic["GetAddressCommands"]];
GetAddressDoneBA: Node _ NodeCreateHack1["GetAddressDoneBA"];
LatchSharedAB: Node _ NodeCreateHack1["LatchSharedAB"];
IsNoOpBA: Node _ NodeCreateHack1["IsNoOpBA"];
IsCleanBA: Node _ NodeCreateHack1["IsCleanBA"];
MatchRealBA: Node _ NodeCreateHack1["MatchRealBA"];
MAdrHigh: Node _ NodeCreateHack1["MAdrHigh"];
[] _ RoseCreate.CreateCell[within: thisCell, instanceName: "mCtlSequencer", className: "MCtlSequencer", interfaceNodes: ""];
[] _ RoseCreate.CreateCell[within: thisCell, instanceName: "mCtlEntryCtl", className: "MCtlEntryCtl", interfaceNodes: ""];
[] _ RoseCreate.CreateCell[within: thisCell, instanceName: "mCtlFlagCtl", className: "MCtlFlagCtl", interfaceNodes: ""];
[] _ RoseCreate.CreateCell[within: thisCell, instanceName: "mCtlRAMCtl", className: "MCtlRAMCtl", interfaceNodes: ""];
[] _ RoseCreate.CreateCell[within: thisCell, instanceName: "mCtlCAMCtl", className: "MCtlCAMCtl", interfaceNodes: ""];
};

CreateMCtlIO: IOCreator = {
cell.realCellStuff.switchIO _ NEW [MCtlIORec];
cell.realCellStuff.newIO _ NEW [MCtlIORec];
cell.realCellStuff.oldIO _ NEW [MCtlIORec];
};

MCtlPorts: Ports _ NEW [PortsRep[127]];

RegisterCells[];

END.
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