-- DragonDetails.tioga 
-- Last Edited by: Barth, April 30, 1984 5:57:32 pm PDT

1 The arbiter must drive MCmd to NoOp when no master has the bus, could also control MNewRq.
2 The cache needs to implement flow control in WriteQuad.
3 Should the upper order 2 bits of the address be ignored?  Should the bits used to break up the address space be restricted to the 
low and high order 2 page bits?
4 With mapping being done with IO commands it is difficult for all caches to listen in on a map request and set their rpdirty bits 
from it.  This means that as a page goes dirty each cache will find out about it independently even the information is actually 
broadcast to them all.
5 Could proceed with Read-Modify-Write to block that is not shared without MGnt if cache can hold off ReadQuad to that block with 
MReady until Write completes.
6 Put a state machine in so that if TIP set but word actually already in then the request is allowed to complete.
-7 Precharge PRejectB and PFaultB low during PhA.
-8 Don't allow stores during rejects or faults, either inhibit selection or driving the bit lines.
-9 Make simulation correspond to layout logic, e.g. Resetb causes data select and the proper data must be put onto the vpValid, 
rpValid and ? flag lines, change to shift on miss philosophy, put in correct control lines for that, use PhBb and PhAb all over the 
place as well.