CachePRAMDriver.rose
Last edited by: Barth, May 14, 1984 8:20:25 pm PDT
Imports BitOps, BitSwOps, Dragon;
Open BitOps, BitSwOps, Dragon;
PRAMDriver: CELL[
Timing and housekeeping interface
Vdd, Gnd<BOOL,
LatchBias<BOOL,
RAM access
PBits, nPBits=SWITCH[66]-S-X,
Debug interface
ShiftDataToMCtlPads>BOOL,
Internal processor interface
PDataI=INT[32],
PParityI=BOOL,
More debug interface
ShiftFeedBack, nShiftFeedBack, ShiftEqual, nShiftEqual, ShiftShift, nShiftShift<BOOL,
ShiftDataToPRAMDriver<BOOL,
PRAMDriver interface
nPBitsPrecharge, MuxRight, MuxLeft, PBitsDrive, nPBitsDrive, PRamRegToPDataI, nPRamRegToPDataI, SensePBits, SensePDataI, ParityIn<BOOL,
ParityOut>BOOL,
ReadPRAMReg, nReadPRAMReg<BOOL
]
State
shiftData, nshiftData: BitDWord,
pRAMReg: BitDWord,
parityShift, nparityShift: BOOL,
pRAMRegParity: BOOL
EvalSimple
Assert[NOT MoreThanOneOf[MuxRight, MuxLeft]];
Assert[NOT MoreThanOneOf[PBitsDrive, nPBitsDrive]];
Assert[NOT MoreThanOneOf[PRamRegToPDataI, nPRamRegToPDataI]];
Assert[NOT MoreThanOneOf[SensePBits, SensePDataI]];
Assert[NOT MoreThanOneOf[NOT nPBitsPrecharge, PBitsDrive]];
Assert[NOT MoreThanOneOf[PBitsDrive, SensePBits]];
Assert[NOT MoreThanOneOf[PRamRegToPDataI, SensePDataI]];
Assert[NOT MoreThanOneOf[ShiftFeedBack, ShiftShift, ReadPRAMReg]];
Assert[NOT MoreThanOneOf[ShiftFeedBack, nShiftFeedBack]];
Assert[NOT MoreThanOneOf[ShiftEqual, nShiftEqual]];
Assert[NOT MoreThanOneOf[ShiftShift, nShiftShift]];
Assert[NOT MoreThanOneOf[ReadPRAMReg, nReadPRAMReg]];
Assert[NOT ParityIn];
IF ShiftShift THEN {
nshiftData ← MDTD[DNOT[shiftData, 32], 32, 0, 31, nshiftData, 32, 1, 31];
nshiftData ← IBID[NOT ShiftDataToPRAMDriver, nshiftData, 32, 0];
nparityShift ← NOT EBFD[shiftData, 32, 31];
};
IF ShiftFeedBack THEN {
nshiftData ← MDTD[DNOT[shiftData, 32], 32, 0, 32, nshiftData, 32, 0, 32];
nparityShift ← NOT parityShift;
};
IF ShiftEqual THEN {
shiftData ← MDTD[DNOT[nshiftData, 32], 32, 0, 32, shiftData, 32, 0, 32];
ShiftDataToMCtlPads ← parityShift ← NOT nparityShift;
};
IF ShiftShift AND ShiftEqual THEN {
FOR i: CARDINAL IN [0..32) DO
shiftData ← IBID[ShiftDataToPRAMDriver, shiftData, 32, i];
ENDLOOP;
FOR i: CARDINAL IN [0..32) DO
nshiftData ← IBID[NOT ShiftDataToPRAMDriver, nshiftData, 32, i];
ENDLOOP;
parityShift ← ShiftDataToPRAMDriver;
nparityShift ← NOT ShiftDataToPRAMDriver;
};
IF SensePDataI THEN {
pRAMReg ← PDataI;
pRAMRegParity ← PParityI;
};
TRUSTED {
pbitd: SwitchMWord ← DESCRIPTOR[PBits];
npbitd: SwitchMWord ← DESCRIPTOR[nPBits];
s: SwitchTypes.Strength ← IF PBitsDrive THEN driveStrong ELSE none;
offset: CARDINAL ← IF MuxLeft THEN 0 ELSE 1;
FOR i:CARDINAL IN [0..32) DO
SIBIS[EBFD[pRAMReg, 32, i], pbitd, 66, (2*i)+offset, [[s, L], [s, H]]];
SIBIS[EBFD[pRAMReg, 32, i], npbitd, 66, (2*i)+offset, [[s, H], [s, L]]];
SIBIS[FALSE, pbitd, 66, (2*i)+1-offset, [[none, X], [none, X]]];
SIBIS[FALSE, npbitd, 66, (2*i)+1-offset, [[none, X], [none, X]]];
ENDLOOP;
SIBIS[pRAMRegParity, pbitd, 66, 64+offset, [[s, L], [s, H]]];
SIBIS[pRAMRegParity, npbitd, 66, 64+offset, [[s, H], [s, L]]];
SIBIS[FALSE, pbitd, 66, 65-offset, [[none, X], [none, X]]];
SIBIS[FALSE, npbitd, 66, 65-offset, [[none, X], [none, X]]];
IF NOT nPBitsPrecharge THEN {
SCDTS[BitDWordOnes, 32, 0, 32, pbitd, 66, 0, 32, [[none, X], [drive, H]]];
SCDTS[BitDWordOnes, 32, 0, 32, npbitd, 66, 0, 32, [[none, X], [drive, H]]];
SCDTS[BitDWordOnes, 32, 0, 32, pbitd, 66, 32, 32, [[none, X], [drive, H]]];
SCDTS[BitDWordOnes, 32, 0, 32, npbitd, 66, 32, 32, [[none, X], [drive, H]]];
SCWTS[BitWordOnes, 16, 0, 2, pbitd, 66, 64, 2, [[none, X], [drive, H]]];
SCWTS[BitWordOnes, 16, 0, 2, npbitd, 66, 64, 2, [[none, X], [drive, H]]];
};
IF SensePBits THEN {
FOR i:CARDINAL IN [0..32) DO
pRAMReg ← IBID[EBFS[pbitd, 66, (2*i)+offset], pRAMReg, 32, i];
ENDLOOP;
pRAMRegParity ← EBFS[pbitd, 66, 64+offset];
};
};
IF ReadPRAMReg THEN {
nshiftData ← DNOT[pRAMReg, 32];
nparityShift ← NOT pRAMRegParity;
};
ParityOut ← ParityIn;
FOR j:CARDINAL IN [0..32) DO
IF EBFD[pRAMReg, 32, j] THEN ParityOut ← NOT ParityOut;
ENDLOOP;
IF pRAMRegParity THEN ParityOut ← NOT ParityOut;
IF PRamRegToPDataI THEN {
PDataI ← pRAMReg;
PParityI ← pRAMRegParity;
};
ENDCELL