<<[Indigo]Cache>Rosemary>Cache.df=>CacheMicroCode.Mesa>> <> DIRECTORY CacheMicroMachine; CacheMicroCode: CEDAR PROGRAM IMPORTS CacheMicroMachine = BEGIN OPEN CacheMicroMachine; <> <> <> <> < page and block access lines>> < page and block match register>> < page access lines and block virtual lines>> < page and block virtual lines>> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> < not VirtualAccess, SelVictimAdr>> < none>> < not VirtualAccess, SelMapAdr>> < none>> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> Slave; Sequence[0]; -- DataTransport(0), IORead(5), IOReadDone(6), IOWrite(7), IOWriteDone(8), Reserve9(9), Reserve10(10), Reserve11(11), Reserve12(12), Reserve13(13), Reserve14(14), NoOp(15) Cycle[0, LIST[$MDataToMDataI, $MDataIToMatchReg, $MDataIToMAdrCtr, $MDataIToMRAMReg, $MDataIToFaults, $MCmdInToCmd, $GetAddress, $Refresh, $RefreshCtrToMAdrLow, $PrechargeMNShared, $Done]]; Sequence[1]; -- ReadQuad(1) Cycle[0, LIST[$DriveShared, $SetShared, $SelRealData, $MAdrCtrToMAdr, $MBitsToMRAMReg, $MRAMRegToMDataI]]; Cycle[1, LIST[$DriveMData, $IncMAdrCtrToMAdr, $SelRealData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]]; Cycle[2, LIST[$DriveMData, $IncMAdrCtrToMAdr, $SelRealData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]]; Cycle[3, LIST[$DriveMData, $IncMAdrCtrToMAdr, $SelRealData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]]; Cycle[4, LIST[$DriveMData, $CheckParity, $GetAddress, $Refresh, $RefreshCtrToMAdrLow, $Done, $ForceIdle]]; Sequence[2]; -- WriteQuad(2) Cycle[0, LIST[$ZeroMAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData]]; Cycle[1, LIST[$IncMAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData, $CheckParity]]; Cycle[2, LIST[$IncMAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData, $CheckParity]]; Cycle[3, LIST[$IncMAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData, $CheckParity, $DCheckParity, $GetAddress, $Done, $ForceIdle]]; Sequence[3]; -- WriteSingle(3) Cycle[1, LIST[$MAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData, $DCheckParity, $GetAddress, $Done, $ForceIdle]]; Sequence[4]; -- ChangeFlags(4) Cycle[1, LIST[$SuppressFlagLatch, $SelPageFlag, $RPDirtyVPValid, $Done, $ForceIdle]]; Master; Sequence[0]; -- WriteQuad Cycle[0, LIST[$GetAddress]]; Cycle[1, LIST[$DriveMCmd, $PageAccessToMDataI, $LowBitsAccessToMDataI, $MDataIToMData, $DriveMData, $SelVictimData, $ZeroMAdrCtrToMAdr, $MBitsToMRAMReg, $MRAMRegToMDataI, $NextCmd]]; Cycle[2, LIST[$DriveMCmdToDataTransport, $DriveMData, $IncMAdrCtrToMAdr, $SelVictimData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]]; Cycle[3, LIST[$DriveMCmdToDataTransport, $DriveMData, $IncMAdrCtrToMAdr, $SelVictimData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]]; Cycle[4, LIST[$DriveMCmdToDataTransport, $DriveMData, $IncMAdrCtrToMAdr, $SelVictimData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]]; Cycle[5, LIST[$DriveMCmdToDataTransport, $DriveMData, $CheckParity, $GetAddress, $Refresh, $RefreshCtrToMAdrLow, $Done]]; Sequence[1]; -- IORead, map operation Cycle[0, LIST[$GetAddress]]; Cycle[1, LIST[$DriveMCmd, $PageAccessToMDataI, $MapBitsToMDataI, $MDataIToMData, $DriveMData, $ForceSlave, $ForceIdle, $Done]]; Cycle[2, LIST[$NextCmd, $CheckFaults, $GetAddress, $Refresh, $RefreshCtrToMAdrLow, $Done, $MDone]]; Sequence[2]; -- ReadQuad Cycle[0, LIST[$GetAddress]]; Cycle[1, LIST[$DriveMCmd, $PageAccessToMDataI, $LowBitsAccessToMDataI, $MDataIToMData, $DriveMData, $AccessToMatch, $PAdrToMAdrCtr, $NextCmd, $Refresh, $RefreshCtrToMAdrLow]]; Cycle[2, LIST[]]; Cycle[3, LIST[]]; Cycle[4, LIST[]]; Cycle[5, LIST[]]; Cycle[6, LIST[]]; Sequence[3]; -- WriteSingle Cycle[0, LIST[$GetAddress]]; Cycle[1, LIST[]]; Cycle[2, LIST[]]; Sequence[4]; -- IORead, real io operation Cycle[1, LIST[$GetAddress]]; Cycle[2, LIST[]]; Sequence[5]; -- IOWrite Cycle[1, LIST[$GetAddress]]; Cycle[2, LIST[]]; END.