[Indigo]<Dragon>Cache>Rosemary>CacheMicroCode.mesa!1

[Indigo]<Dragon>Cache>Rosemary>Cache.df=>CacheMicroCode.Mesa

Last Edited by: Barth, March 14, 1984 12:21:36 pm PST

DIRECTORY CacheMicroMachine;

CacheMicroCode: CEDAR PROGRAM

IMPORTS CacheMicroMachine =

BEGIN OPEN CacheMicroMachine;

The first letter in each line indicates the timing of the line. If it is B then it the line is decoded from the state lines which combinatorially follow the bus lines during A and so the line actually fires during PhB. If it is A then the line decodes from the state lines which are one phase pipelined from the bus so that the action associated with the line is done during PhA. If it is C then the line is decoded from the same state lines as B but the signal is driven throughout both PhB and PhA. This takes a funny circuit described in /Cherry/Barth/Dragon/Cache/Sil/MBusDecoder.sil. If none of A, B or C appear then the timing situation is more complicated and is described with the functional description of the signal which follows after the line name.

MCtlCAMCtl

A MDataIToMatchReg causes MDataToMatch.

A GetAddress(MCtlEntryCtl) causes the command on GetAdrCmd to be interpreted and the resulting address to be loaded into the access register:

VictimReal => page and block access lines

RefRealMap => page and block match register

RefRealAssemble => page access lines and block virtual lines

RefVirtual => page and block virtual lines

B PageAccessToMDataI causes the access register to be driven onto MDataI[0..23].

B LowBitsAccessToMDataI causes the access register to be driven onto MDataI[24..29].

A AccessToMatch causes the match register to be loaded from the access register.

MCtlRAMCtl

A MDataIToMRAMReg causes SenseMDataI.

A MBitsToMRAMReg causes SenseMBits. It is possible that this line and the next could be turned into one decode.

A MRAMRegToMDataI causes MRamRegToMDataI.

A MRAMRegToMBits causes MBitsDrive.

MCtlFlagCtl

A SetShared sets the shared flag bit line.

A RPDirtyVPValid causes the RPDirty and VPValid bits sampled from MData to be driven onto the flag access lines.

B SuppressFlagLatch suppresses the latching of flag bits from MData which normally occurs every PhA.

MCtlEntryCtl

A MDataIToMAdrCtr causes the two low order bits of the address to be loaded into the address counter.

A GetAddress(MCtlCAMCtl) causes the command on GetAdrCmd to be interpreted and the appropriate select lines to the cells to be asserted:

VictimReal => not VirtualAccess, SelVictimAdr

RefRealMap => none

RefRealAssemble => not VirtualAccess, SelMapAdr

RefVirtual => none

A Refresh causes SelCell. On cycles where both GetAddress and Refresh occur GetAddress has precedence unless the signal DoRefresh is asserted or the MasterCmd is a NoOp in which case Refresh wins. If GetAdrCmd is RefVirtual then both Refresh and GetAddress can occur on the same cycle. DoRefresh is driven by a counter which counts cycles since the last refresh, it is reset each time a refresh actually occurs. This means that a GetAddress may not have happened when a master is about to start, if this is the case then the cycle counter will be set to zero instead of one and the prefetch command should be asserted again, without refresh being a possibility.

RefreshCtrToMAdrLow causes the refresh counter to be sent to MAdrLow and nMAdrLow. If the decoder in the cells is setup appropriately then one of these can be sent high during PhA to cause the appropriate word line to go high. If the decoder in the cells is not setup appropriately then RefreshCtrToMAdr will have to be decoded during PhB and the address sent during PhB so that those lines are stable prior to PhA starting.

MAdrCtrToMAdr causes the bits in the address counter to be applied to MAdrHigh and MAdrLow. This has the same timing as RefreshCtrToMAdrLow.

IncMAdrCtrToMAdr causes the bits in the incremented address counter to be applied to MAdrHigh and MAdrLow . This has the same timing as RefreshCtrToMAdrLow, i.e. happens during A if the decoder in the cells is set up right.

ZeroMAdrCtrToMAdr causes the bits in the address counter zeroed and zeros to be applied to MAdrHigh and MAdrLow . This has the same timing as RefreshCtrToMAdrLow.

A PAdrToMAdrCtr causes address counter to be loaded from the address bits supplied by the P controller.

B LowBitsAccessToMDataI causes the address counter to be driven onto MDataI[30..31].

A SelRealData causes the cell matching the page and block match registers to be selected.

A SelPageFlag causes the RPDirty and VPValid bits of the entries which match the page match register to be selected.

A SelVictimData causes the cell with the victim bit to select a data word and its flag bits.

MCtlSequencer

A MDataIToFaults causes the three low order bits of the data bus to be loaded into the fault type register.

MCmdInToCmd causes the recoded MCmdIn to be sampled into the sequence latch and cycle number set to zero during PhA. The sequence number and cycle number are then transmitted to the pipelined state lines during the next PhB. When IOReadDone is seen and ForceSlave is true then Master is combinatorially set true, the sequence is set back to whatever the entry point sequencer is set to and the cycle is set to 2.

C MDataToMDataI causes MData to be driven onto MDataI.

C DriveShared enables MNShared to be driven low if some cell matched on the block address.

A PrechargeMNShared causes MNShared to be precharged. Note that this happens for only half a cycle. Also note that everything hanging on the MBus precharges this line so that should not be any problem.

B MDataIToMData causes the pipeline in the pad data register to be bypassed so that the register loaded during PhB is loaded directly from MDataI. Every PhA the pad data register is loaded from MDataI. Every PhB the first stage register is moved into the second stage register. The thought is that the data will transfer to the actual pad enables at about the same time in every cache when doing a slave ReadQuad so that no set of caches are ever pulling in opposite directions on the bus.

C DriveMData causes MData to be driven from the pad register if the RealMatch register is true or grant is true.

C DriveMCmd causes MCmd to be driven from the command being output by the entry point sequencer. It was previously placed on MCmdOut, this line need only assert DriveMCmdOut.

C DriveMCmdToDataTransport causes MCmd to be driven to DataTransport.

B CheckParity causes the check of the parity bit from MRAMReg to be latched. The error latch is set if the check is bad on the following PhA.

A DCheckParity causes a parity check during the following PhB instead of during the current PhB.

A Done causes the cycle to be forced to zeros. If grant is seen during a PhA that Done is asserted and ForceSlave is not asserted then the cycle depends upon whether GetAddress was successful in loading the master commands address into the access register of the MCAMDriver. If it was then the cycle is set to 1 else it is set to 0. The sequence is forced to be whatever the entry point sequencer is saying it ought to be regardless of ForceIdle. This computation has less precedence than that which forces the sequence and cycle due to MCmdInToCmd.

A ForceIdle causes the sequence to be forced to zeros.

A NextCmd causes the entry point sequencer to change to the next entry point and to change GetAdrCmd to the appropriate value for that command.

B MapBitsToMDataI causes the appropriate bits to get the correct map operation done to be placed on MDataI[24..31].

A ForceSlave causes slave to be sent in the state even though the cache is retaining the M bus.

A CheckFaults causes the fault lines to P to be driven from the bits latched from MDataI and if there is a fault causes the entry point sequencer to go idle, i.e. forces MasterCmd to a noop.

A MDone causes MDone to be sent to the P controller if the entry point sequencer is idle. Note that NextCmd may occur in the same cycle as MDone in which case idleness should be computed before deciding not to assert MDone.

Slave;

Sequence[0]; -- DataTransport(0), IORead(5), IOReadDone(6), IOWrite(7), IOWriteDone(8), Reserve9(9), Reserve10(10), Reserve11(11), Reserve12(12), Reserve13(13), Reserve14(14), NoOp(15)

Cycle[0, LIST[$MDataToMDataI, $MDataIToMatchReg, $MDataIToMAdrCtr, $MDataIToMRAMReg, $MDataIToFaults, $MCmdInToCmd, $GetAddress, $Refresh, $RefreshCtrToMAdrLow, $PrechargeMNShared, $Done]];

Sequence[1]; -- ReadQuad(1)

Cycle[0, LIST[$DriveShared, $SetShared, $SelRealData, $MAdrCtrToMAdr, $MBitsToMRAMReg, $MRAMRegToMDataI]];

Cycle[1, LIST[$DriveMData, $IncMAdrCtrToMAdr, $SelRealData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]];

Cycle[2, LIST[$DriveMData, $IncMAdrCtrToMAdr, $SelRealData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]];

Cycle[3, LIST[$DriveMData, $IncMAdrCtrToMAdr, $SelRealData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]];

Cycle[4, LIST[$DriveMData, $CheckParity, $GetAddress, $Refresh, $RefreshCtrToMAdrLow, $Done, $ForceIdle]];

Sequence[2]; -- WriteQuad(2)

Cycle[0, LIST[$ZeroMAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData]];

Cycle[1, LIST[$IncMAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData, $CheckParity]];

Cycle[2, LIST[$IncMAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData, $CheckParity]];

Cycle[3, LIST[$IncMAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData, $CheckParity, $DCheckParity, $GetAddress, $Done, $ForceIdle]];

Sequence[3]; -- WriteSingle(3)

Cycle[1, LIST[$MAdrCtrToMAdr, $MDataToMDataI, $MDataIToMRAMReg, $MRAMRegToMBits, $SelRealData, $DCheckParity, $GetAddress, $Done, $ForceIdle]];

Sequence[4]; -- ChangeFlags(4)

Cycle[1, LIST[$SuppressFlagLatch, $SelPageFlag, $RPDirtyVPValid, $Done, $ForceIdle]];

Master;

Sequence[0]; -- WriteQuad

Cycle[0, LIST[$GetAddress]];

Cycle[1, LIST[$DriveMCmd, $PageAccessToMDataI, $LowBitsAccessToMDataI, $MDataIToMData, $DriveMData, $SelVictimData, $ZeroMAdrCtrToMAdr, $MBitsToMRAMReg, $MRAMRegToMDataI, $NextCmd]];

Cycle[2, LIST[$DriveMCmdToDataTransport, $DriveMData, $IncMAdrCtrToMAdr, $SelVictimData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]];

Cycle[3, LIST[$DriveMCmdToDataTransport, $DriveMData, $IncMAdrCtrToMAdr, $SelVictimData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]];

Cycle[4, LIST[$DriveMCmdToDataTransport, $DriveMData, $IncMAdrCtrToMAdr, $SelVictimData, $MBitsToMRAMReg, $MRAMRegToMDataI, $CheckParity]];

Cycle[5, LIST[$DriveMCmdToDataTransport, $DriveMData, $CheckParity, $GetAddress, $Refresh, $RefreshCtrToMAdrLow, $Done]];

Sequence[1]; -- IORead, map operation

Cycle[0, LIST[$GetAddress]];

Cycle[1, LIST[$DriveMCmd, $PageAccessToMDataI, $MapBitsToMDataI, $MDataIToMData, $DriveMData, $ForceSlave, $ForceIdle, $Done]];

Cycle[2, LIST[$NextCmd, $CheckFaults, $GetAddress, $Refresh, $RefreshCtrToMAdrLow, $Done, $MDone]];

Sequence[2]; -- ReadQuad

Cycle[0, LIST[$GetAddress]];

Cycle[1, LIST[$DriveMCmd, $PageAccessToMDataI, $LowBitsAccessToMDataI, $MDataIToMData, $DriveMData, $AccessToMatch, $PAdrToMAdrCtr, $NextCmd, $Refresh, $RefreshCtrToMAdrLow]];

Cycle[2, LIST[]];

Cycle[3, LIST[]];

Cycle[4, LIST[]];

Cycle[5, LIST[]];

Cycle[6, LIST[]];

Sequence[3]; -- WriteSingle

Cycle[0, LIST[$GetAddress]];

Cycle[1, LIST[]];

Cycle[2, LIST[]];

Sequence[4]; -- IORead, real io operation

Cycle[1, LIST[$GetAddress]];

Cycle[2, LIST[]];

Sequence[5]; -- IOWrite

Cycle[1, LIST[$GetAddress]];

Cycle[2, LIST[]];

END.