--CacheMRAMDriver.Mesa --created by RoseTranslate from CacheMRAMDriver.Rose of May 15, 1984 9:58:34 am PDT for Barth.pa at May 15, 1984 10:00:26 am PDT DIRECTORY RoseTypes, RoseCreate, BitOps, BitSwOps, Dragon, SwitchTypes; CacheMRAMDriver: CEDAR PROGRAM IMPORTS RoseCreate, BitOps, BitSwOps, Dragon = BEGIN OPEN RoseTypes, BitOps, BitSwOps, Dragon; --Signal Type decls RegisterCells: PROC = BEGIN CreateMRAMDriverPorts[]; [] _ RoseCreate.RegisterCellClass[className: "MRAMDriver", expandProc: NIL, ioCreator: CreateMRAMDriverIO, initializer: InitializeMRAMDriver, evals: [EvalSimple: MRAMDriverEvalSimple], blackBox: NIL, stateToo: NIL, ports: MRAMDriverPorts, drivePrototype: NEW [MRAMDriverDrive]]; END; CreateMRAMDriverPorts: PROC = {MRAMDriverPorts _ RoseCreate.PortsFromFile["CacheMRAMDriver.MRAMDriver.rosePorts"]}; MRAMDriverIORef: TYPE = REF MRAMDriverIORec; MRAMDriverIORec: TYPE = MACHINE DEPENDENT RECORD [ fill0(0:0..14): [0..32767], Vdd(0:15..15): BOOLEAN, fill1(1:0..14): [0..32767], Gnd(1:15..15): BOOLEAN, fill2(2:0..14): [0..32767], LatchBias(2:15..15): BOOLEAN, PBits(3:0..1055): PACKED ARRAY [0 .. 65] OF SwitchTypes.SwitchVal, nPBits(69:0..1055): PACKED ARRAY [0 .. 65] OF SwitchTypes.SwitchVal, MBits(135:0..1055): PACKED ARRAY [0 .. 65] OF SwitchTypes.SwitchVal, nMBits(201:0..1055): PACKED ARRAY [0 .. 65] OF SwitchTypes.SwitchVal, MDataI(267:0..31): ARRAY [0..2) OF CARDINAL, fill8(269:0..14): [0..32767], MParityI(269:15..15): BOOLEAN, fill9(270:0..14): [0..32767], ShiftDataToMRAM(270:15..15): BOOLEAN, fill10(271:0..14): [0..32767], ShiftDataToMCtl(271:15..15): BOOLEAN, fill11(272:0..14): [0..32767], ShiftFeedBack(272:15..15): BOOLEAN, fill12(273:0..14): [0..32767], nShiftFeedBack(273:15..15): BOOLEAN, fill13(274:0..14): [0..32767], ShiftEqual(274:15..15): BOOLEAN, fill14(275:0..14): [0..32767], nShiftEqual(275:15..15): BOOLEAN, fill15(276:0..14): [0..32767], ShiftShift(276:15..15): BOOLEAN, fill16(277:0..14): [0..32767], nShiftShift(277:15..15): BOOLEAN, fill17(278:0..14): [0..32767], nMBitsPrecharge(278:15..15): BOOLEAN, fill18(279:0..14): [0..32767], MuxRight(279:15..15): BOOLEAN, fill19(280:0..14): [0..32767], MuxLeft(280:15..15): BOOLEAN, fill20(281:0..14): [0..32767], MBitsDrive(281:15..15): BOOLEAN, fill21(282:0..14): [0..32767], nMBitsDrive(282:15..15): BOOLEAN, fill22(283:0..14): [0..32767], MRamRegToMDataI(283:15..15): BOOLEAN, fill23(284:0..14): [0..32767], nMRamRegToMDataI(284:15..15): BOOLEAN, fill24(285:0..14): [0..32767], SenseMBits(285:15..15): BOOLEAN, fill25(286:0..14): [0..32767], SenseMDataI(286:15..15): BOOLEAN, fill26(287:0..14): [0..32767], ParityIn(287:15..15): BOOLEAN, fill27(288:0..14): [0..32767], ParityOut(288:15..15): BOOLEAN, fill28(289:0..14): [0..32767], SensePBitsLeft(289:15..15): BOOLEAN, fill29(290:0..14): [0..32767], SensePBitsRight(290:15..15): BOOLEAN, fill30(291:0..14): [0..32767], DrivePBits(291:15..15): BOOLEAN, fill31(292:0..14): [0..32767], nDrivePBits(292:15..15): BOOLEAN, fill32(293:0..14): [0..32767], MRamRegToMBits(293:15..15): BOOLEAN, fill33(294:0..14): [0..32767], nMRamRegToMBits(294:15..15): BOOLEAN, fill34(295:0..14): [0..32767], ShiftToMBits(295:15..15): BOOLEAN, fill35(296:0..14): [0..32767], nShiftToMBits(296:15..15): BOOLEAN, fill36(297:0..14): [0..32767], MBitsToShift(297:15..15): BOOLEAN, fill37(298:0..14): [0..32767], nMBitsToShift(298:15..15): BOOLEAN]; -- port indices: MRAMDriverPBitsPortIndex: CARDINAL = 3; MRAMDriverNPBitsPortIndex: CARDINAL = 4; MRAMDriverMBitsPortIndex: CARDINAL = 5; MRAMDriverNMBitsPortIndex: CARDINAL = 6; MRAMDriverDrive: TYPE = MACHINE DEPENDENT RECORD [ fill0(0:0..14): [0 .. 32768), Vdd(0:15..15): BOOLEAN, fill1(1:0..14): [0 .. 32768), Gnd(1:15..15): BOOLEAN, fill2(2:0..14): [0 .. 32768), LatchBias(2:15..15): BOOLEAN, fill3(3:0..14): [0 .. 32768), PBits(3:15..15): BOOLEAN, fill4(4:0..14): [0 .. 32768), nPBits(4:15..15): BOOLEAN, fill5(5:0..14): [0 .. 32768), MBits(5:15..15): BOOLEAN, fill6(6:0..14): [0 .. 32768), nMBits(6:15..15): BOOLEAN, fill7(7:0..14): [0 .. 32768), MDataI(7:15..15): BOOLEAN, fill8(8:0..14): [0 .. 32768), MParityI(8:15..15): BOOLEAN, fill9(9:0..14): [0 .. 32768), ShiftDataToMRAM(9:15..15): BOOLEAN, fill10(10:0..14): [0 .. 32768), ShiftDataToMCtl(10:15..15): BOOLEAN, fill11(11:0..14): [0 .. 32768), ShiftFeedBack(11:15..15): BOOLEAN, fill12(12:0..14): [0 .. 32768), nShiftFeedBack(12:15..15): BOOLEAN, fill13(13:0..14): [0 .. 32768), ShiftEqual(13:15..15): BOOLEAN, fill14(14:0..14): [0 .. 32768), nShiftEqual(14:15..15): BOOLEAN, fill15(15:0..14): [0 .. 32768), ShiftShift(15:15..15): BOOLEAN, fill16(16:0..14): [0 .. 32768), nShiftShift(16:15..15): BOOLEAN, fill17(17:0..14): [0 .. 32768), nMBitsPrecharge(17:15..15): BOOLEAN, fill18(18:0..14): [0 .. 32768), MuxRight(18:15..15): BOOLEAN, fill19(19:0..14): [0 .. 32768), MuxLeft(19:15..15): BOOLEAN, fill20(20:0..14): [0 .. 32768), MBitsDrive(20:15..15): BOOLEAN, fill21(21:0..14): [0 .. 32768), nMBitsDrive(21:15..15): BOOLEAN, fill22(22:0..14): [0 .. 32768), MRamRegToMDataI(22:15..15): BOOLEAN, fill23(23:0..14): [0 .. 32768), nMRamRegToMDataI(23:15..15): BOOLEAN, fill24(24:0..14): [0 .. 32768), SenseMBits(24:15..15): BOOLEAN, fill25(25:0..14): [0 .. 32768), SenseMDataI(25:15..15): BOOLEAN, fill26(26:0..14): [0 .. 32768), ParityIn(26:15..15): BOOLEAN, fill27(27:0..14): [0 .. 32768), ParityOut(27:15..15): BOOLEAN, fill28(28:0..14): [0 .. 32768), SensePBitsLeft(28:15..15): BOOLEAN, fill29(29:0..14): [0 .. 32768), SensePBitsRight(29:15..15): BOOLEAN, fill30(30:0..14): [0 .. 32768), DrivePBits(30:15..15): BOOLEAN, fill31(31:0..14): [0 .. 32768), nDrivePBits(31:15..15): BOOLEAN, fill32(32:0..14): [0 .. 32768), MRamRegToMBits(32:15..15): BOOLEAN, fill33(33:0..14): [0 .. 32768), nMRamRegToMBits(33:15..15): BOOLEAN, fill34(34:0..14): [0 .. 32768), ShiftToMBits(34:15..15): BOOLEAN, fill35(35:0..14): [0 .. 32768), nShiftToMBits(35:15..15): BOOLEAN, fill36(36:0..14): [0 .. 32768), MBitsToShift(36:15..15): BOOLEAN, fill37(37:0..14): [0 .. 32768), nMBitsToShift(37:15..15): BOOLEAN]; MRAMDriverStateRef: TYPE = REF MRAMDriverStateRec; MRAMDriverStateRec: TYPE = RECORD [ mRAMReg, shiftData, nShiftData: BitDWord, mRAMRegParity, shiftDataParity, nShiftDataParity: BOOL ]; CreateMRAMDriverIO: IOCreator = { cell.realCellStuff.switchIO _ NEW [MRAMDriverIORec]; cell.realCellStuff.newIO _ NEW [MRAMDriverIORec]; cell.realCellStuff.oldIO _ NEW [MRAMDriverIORec]; }; InitializeMRAMDriver: Initializer = { IF leafily THEN BEGIN state: MRAMDriverStateRef _ NEW [MRAMDriverStateRec]; cell.realCellStuff.state _ state; END; }; MRAMDriverEvalSimple: CellProc = BEGIN sw: MRAMDriverIORef _ NARROW[cell.realCellStuff.switchIO]; newIO: MRAMDriverIORef _ NARROW[cell.realCellStuff.newIO]; state: MRAMDriverStateRef _ NARROW[cell.realCellStuff.state]; BEGIN OPEN newIO, state; Assert[NOT MoreThanOneOf[NOT nMBitsPrecharge, MBitsDrive]]; Assert[(NOT MBitsDrive) OR (MRamRegToMBits OR ShiftToMBits)]; Assert[MuxRight OR MuxLeft]; Assert[NOT MoreThanOneOf[MuxRight, MuxLeft]]; Assert[NOT MoreThanOneOf[MBitsDrive, nMBitsDrive]]; Assert[NOT MoreThanOneOf[MBitsToShift, nMBitsToShift]]; Assert[NOT MoreThanOneOf[ShiftToMBits, nShiftToMBits]]; Assert[NOT MoreThanOneOf[MRamRegToMDataI, nMRamRegToMDataI]]; Assert[NOT MoreThanOneOf[DrivePBits, nDrivePBits]]; Assert[NOT MoreThanOneOf[ShiftFeedBack, nShiftFeedBack]]; Assert[NOT MoreThanOneOf[ShiftEqual, nShiftEqual]]; Assert[NOT MoreThanOneOf[ShiftShift, nShiftShift]]; Assert[NOT MoreThanOneOf[ShiftShift, ShiftFeedBack, ShiftEqual]]; Assert[NOT MoreThanOneOf[SenseMBits, MBitsDrive]]; TRUSTED { mbitd: SwitchMWord _ DESCRIPTOR[MBits]; nmbitd: SwitchMWord _ DESCRIPTOR[nMBits]; s: SwitchTypes.Strength _ IF MBitsDrive THEN driveStrong ELSE none; mBitData: BitDWord; mBitParity: BOOL; offset: CARDINAL _ IF MuxLeft THEN 0 ELSE 1; IF SenseMDataI THEN { mRAMReg _ MDataI; mRAMRegParity _ MParityI; }; IF MRamRegToMBits THEN { mBitData _ mRAMReg; mBitParity _ mRAMRegParity; } ELSE { -- assume that ShiftToMBits is asserted mBitData _ shiftData; mBitParity _ shiftDataParity; }; FOR i:CARDINAL IN [0..32) DO SIBIS[EBFD[mBitData, 32, i], mbitd, 66, (2*i)+offset, [[s, L], [s, H]]]; SIBIS[EBFD[mBitData, 32, i], nmbitd, 66, (2*i)+offset, [[s, H], [s, L]]]; SIBIS[FALSE, mbitd, 66, (2*i)+1-offset, [[none, X], [none, X]]]; SIBIS[FALSE, nmbitd, 66, (2*i)+1-offset, [[none, X], [none, X]]]; ENDLOOP; SIBIS[mBitParity, mbitd, 66, 64+offset, [[s, L], [s, H]]]; SIBIS[mBitParity, nmbitd, 66, 64+offset, [[s, H], [s, L]]]; SIBIS[FALSE, mbitd, 66, 65-offset, [[none, X], [none, X]]]; SIBIS[FALSE, nmbitd, 66, 65-offset, [[none, X], [none, X]]]; IF NOT nMBitsPrecharge THEN { SCDTS[BitDWordOnes, 32, 0, 32, mbitd, 66, 0, 32, [[none, X], [drive, H]]]; SCDTS[BitDWordOnes, 32, 0, 32, nmbitd, 66, 0, 32, [[none, X], [drive, H]]]; SCDTS[BitDWordOnes, 32, 0, 32, mbitd, 66, 32, 32, [[none, X], [drive, H]]]; SCDTS[BitDWordOnes, 32, 0, 32, nmbitd, 66, 32, 32, [[none, X], [drive, H]]]; SCWTS[BitWordOnes, 16, 0, 2, mbitd, 66, 64, 2, [[none, X], [drive, H]]]; SCWTS[BitWordOnes, 16, 0, 2, nmbitd, 66, 64, 2, [[none, X], [drive, H]]]; }; FOR i:CARDINAL IN [0..32) DO mBitData _ IBID[EBFS[mbitd, 66, (2*i)+offset], mBitData, 32, i]; ENDLOOP; mBitParity _ EBFS[mbitd, 66, 64+offset]; IF SenseMBits THEN { mRAMReg _ mBitData; mRAMRegParity _ mBitParity; }; IF MBitsToShift THEN { nShiftData _ DNOT[mBitData, 32]; nShiftDataParity _ NOT mBitParity; }; }; IF MRamRegToMDataI THEN { MDataI _ mRAMReg; MParityI _ mRAMRegParity; }; TRUSTED { pbitd: SwitchMWord _ DESCRIPTOR[PBits]; npbitd: SwitchMWord _ DESCRIPTOR[nPBits]; s: SwitchTypes.Strength _ IF DrivePBits THEN driveStrong ELSE none; FOR i:CARDINAL IN [0..32) DO SIBIS[EBFD[mRAMReg, 32, i], pbitd, 66, (2*i), [[s, L], [s, H]]]; SIBIS[EBFD[mRAMReg, 32, i], npbitd, 66, (2*i), [[s, H], [s, L]]]; SIBIS[FALSE, pbitd, 66, (2*i)+1, [[none, X], [none, X]]]; SIBIS[FALSE, npbitd, 66, (2*i)+1, [[none, X], [none, X]]]; ENDLOOP; SIBIS[mRAMRegParity, pbitd, 66, 64, [[s, L], [s, H]]]; SIBIS[mRAMRegParity, npbitd, 66, 64, [[s, H], [s, L]]]; SIBIS[FALSE, pbitd, 66, 65, [[none, X], [none, X]]]; SIBIS[FALSE, npbitd, 66, 65, [[none, X], [none, X]]]; IF SensePBitsLeft THEN { pBitData: BitDWord; FOR i:CARDINAL IN [0..32) DO pBitData _ IBID[EBFS[pbitd, 66, 2*i], pBitData, 32, i]; ENDLOOP; mRAMReg _ pBitData; mRAMRegParity _ EBFS[pbitd, 66, 64]; }; IF SensePBitsRight THEN { pBitData: BitDWord; FOR i:CARDINAL IN [0..32) DO pBitData _ IBID[EBFS[pbitd, 66, (2*i)+1], pBitData, 32, i]; ENDLOOP; mRAMReg _ pBitData; mRAMRegParity _ EBFS[pbitd, 66, 65]; }; }; IF ShiftFeedBack THEN { nShiftData _ DNOT[shiftData, 32]; nShiftDataParity _ NOT shiftDataParity }; IF ShiftShift THEN { nShiftData _ MDTD[DNOT[shiftData, 32], 32, 1, 31, nShiftData, 32, 0, 31]; nShiftData _ IBID[NOT shiftDataParity, nShiftData, 32, 31]; nShiftDataParity _ NOT ShiftDataToMRAM }; IF ShiftEqual THEN { shiftDataParity _ NOT nShiftDataParity; shiftData _ DNOT[nShiftData, 32]; ShiftDataToMCtl _ EBFD[shiftData, 32, 0]; }; ParityOut _ ParityIn; FOR j:CARDINAL IN [0..32) DO IF EBFD[mRAMReg, 32, j] THEN ParityOut _ NOT ParityOut; ENDLOOP; IF mRAMRegParity THEN ParityOut _ NOT ParityOut; END; END; MRAMDriverPorts: Ports _ NEW [PortsRep[38]]; RegisterCells[]; END.