MDataPads:
CELL[
Timing and housekeeping interface
Vdd, Gnd<BOOL,
PadVdd, PadGnd<BOOL,
LatchBias<BOOL,
Main memory interface
MDataBA=INT[32],
MParityBA=BOOL,
Buffered timing and housekeeping interface
PhAh<BOOL,
Internal main memory interface
MDataI=INT[32],
MParityI=BOOL,
MDataDrive, MDataIDrive, MDataPipeBypass, MDataPipeTransfer<BOOL
]
State
mPadRegAB, mPadRegBA: BitDWord,
mPadRegParityAB, mPadRegParityBA: BOOL
EvalSimple
Assert[NOT MoreThanOneOf[MDataPipeBypass, MDataPipeTransfer]];
IF PhAh
THEN {
mPadRegAB ← MDataI;
mPadRegParityAB ← MParityI;
};
IF MDataPipeTransfer
THEN {
mPadRegBA ← mPadRegAB;
mPadRegParityBA ← mPadRegParityAB;
};
IF MDataPipeBypass
THEN {
mPadRegBA ← MDataI;
mPadRegParityBA ← MParityI;
};
IF MDataDrive
THEN {
MDataBA ← mPadRegBA;
MParityBA ← mPadRegParityBA;
};
IF MDataIDrive
THEN {
MDataI ← MDataBA;
MParityI ← MParityBA;
};
ENDCELL;
MCtlPads:
CELL[
Timing and housekeeping interface
PhA, PhB<BOOL,
Vdd, Gnd<BOOL,
PadVdd, PadGnd<BOOL,
LatchBias<BOOL,
Main memory interface
MCmdBA=EnumType["Dragon.MBusCommands"],
MNShared=BOOL,
MParityBA=BOOL,
MNError>BOOL,
MReadyBA<BOOL,
MRq>BOOL,
MNewRq=BOOL,
MGnt<BOOL,
Serial debugging interface
All the following signals change during PhA and propagate during the remainder of PhA and PhB, giving an entire clock cycle for them to propagate throughout the machine. Each user must receive them into a latch open during PhB. The effects of changes are intended to happen throughout the following PhA, PhB pair.
ResetAB<BOOL,
DHoldAB<BOOL, -- must be high before testing
DShiftAB<BOOL, -- shift the shift register by 1 bit if ~DNSelect
DExecuteAB<BOOL, -- interpret the content of the shift register if ~DNSelect
DNSelectAB<BOOL, -- if high, hold but don't Execute or Shift
DDataInAB<BOOL, -- sampled during each PhB that DShift is asserted
DDataOutAB=BOOL, -- changes during each PhA following a PhB that DShift is asserted, continues to be driven through the PhB following the PhA it changes
Buffered timing and housekeeping interface
PhAb, nPhAb, PhBb, nPhBb>BOOL,
PhAh, PhBh>BOOL,
Resetb>BOOL,
Debug interface
DoShiftBA, DoExecuteBA, DoHoldBA>BOOL,
ShiftDataToMCtlPads<BOOL,
Internal main memory interface
MCmdIn>EnumType["Dragon.MBusCommands"],
MCmdOutBA<EnumType["Dragon.MBusCommands"],
MCmdDrive<BOOL,
MCmdDriveToDataTransport<BOOL,
MCmdDriveToNoOp<BOOL,
MNSharedSenseBA>BOOL,
MNSharedDriveHigh<BOOL,
MNSharedDriveLow<BOOL,
MNErrorDriveLow<BOOL,
MReadySense>BOOL,
MRqIBA<BOOL,
MNewRqIBA<BOOL,
MNewRqEnableBA<BOOL,
MGntSense>BOOL,
More debug interface
ShiftDataToMRAM>BOOL,
ShiftShift, nShiftShift<BOOL
]
State
shiftAB, shiftBA: BOOL, -- note that these are static bits, unlike the rest of the shift register
doHoldAB: BOOL
EvalSimple
PhAb ← PhA;
nPhAb ← NOT PhA;
PhBb ← PhB;
nPhBb ← NOT PhB;
IF PhBb
THEN {
Resetb ← ResetAB;
DoHoldBA ← DHoldAB;
DoShiftBA ← DShiftAB AND NOT DNSelectAB;
DoExecuteBA ← DExecuteAB AND NOT DNSelectAB;
shiftBA ← DDataInAB;
};
ShiftDataToMRAM ← shiftBA;
IF ShiftShift THEN shiftAB ← ShiftDataToMCtlPads;
IF NOT DNSelectAB THEN DDataOutAB ← shiftAB;
IF PhAb THEN doHoldAB ← DoHoldBA;
PhAh ← PhAb AND NOT DoHoldBA;
PhBh ← PhBb AND NOT doHoldAB;
MCmdIn ← MCmdBA;
IF MCmdDrive THEN MCmdBA ← MCmdOutBA;
IF MCmdDriveToDataTransport THEN MCmdBA ← DataTransport;
IF MCmdDriveToNoOp THEN MCmdBA ← NoOp;
MNSharedSenseBA ← MNShared;
IF MNSharedDriveHigh THEN MNShared ← TRUE;
IF MNSharedDriveLow THEN MNShared ← FALSE;
IF MNErrorDriveLow THEN MNError ← FALSE;
MReadySense ← MReadyBA;
MRq ← MRqIBA;
IF MNewRqEnableBA THEN MNewRq ← MNewRqIBA;
MGntSense ← MGnt;
ENDCELL