MInterface:
CELL[
Timing and housekeeping interface
PhA, PhB<BOOL,
Vdd, Gnd<BOOL,
PadVdd, PadGnd<BOOL,
LatchBias<BOOL,
Main memory interface
MDataBA=INT[32],
MCmdBA=EnumType["Dragon.MBusCommands"],
MNShared=BOOL,
MParityBA=BOOL,
MNError>BOOL,
MReadyBA<BOOL,
MRq>BOOL,
MNewRq=BOOL,
MGnt<BOOL,
Serial debugging interface
All the following signals change during PhA and propagate during the remainder of PhA and PhB, giving an entire clock cycle for them to propagate throughout the machine. Each user must receive them into a latch open during PhB. The effects of changes are intended to happen throughout the following PhA, PhB pair.
ResetAB<BOOL,
DHoldAB<BOOL, -- must be high before testing
DShiftAB<BOOL, -- shift the shift register by 1 bit if ~DNSelect
DExecuteAB<BOOL, -- interpret the content of the shift register if ~DNSelect
DNSelectAB<BOOL, -- if high, hold but don't Execute or Shift
DDataInAB<BOOL, -- sampled during each PhB following a PhB that DShift is asserted
DDataOutAB=BOOL, -- changes during each PhA following a PhB that DShift is asserted, continues to be driven through the PhB following the PhA it changes
Buffered timing and housekeeping interface
PhAb, nPhAb, PhBb, nPhBb>BOOL,
PhAh, PhBh>BOOL,
Resetb>BOOL,
CAM interface
VirtualPage<INT[24],
VirtualBlock<INT[6],
RealPage, nRealPage>INT[24],
RealBlock, nRealBlock>INT[6],
CAMPageAccess, nCAMPageAccess=SWITCH[24],
CAMBlockAccess, nCAMBlockAccess=SWITCH[6],
RAM access
PBits, nPBits=SWITCH[66],
MBits, nMBits=SWITCH[66],
Cell control
nVirtualMatch, nMatchPageClean, nMatchCellShared=BOOL,
nMapValid, nRealMatch, nVictimClean=BOOL,
CellAdr, nCellAdr>INT[8],
VirtualAccess, nVirtualAccess, SelCell, SelVictimAdr, SelMapAdr, SelRealData, SelPageFlag, SelVictimData, SelRealAdr>BOOL,
FinishSharedStore>BOOL,
VPValid, nVPValid, RPValid, nRPValid, RPDirty, nRPDirty, Master, nMaster, Shared, nShared, Victim, nVictim, TIP, nTIP, Broken, nBroken=BIT,
MAdrLow, nMAdrLow>BOOL,
VictimFeedback, nVictimFeedback, ShiftVictim, nShiftVictim>BOOL,
ForceDataSelect>BOOL,
P control <=> M control
MDoneAB, MHeldAB>BOOL,
MFaultAB>EnumType["Dragon.PBusFaults"],
PAdrHigh, PAdrLowToM<BOOL,
PCmdToMAB<EnumType["Dragon.PBusCommands"],
Debug interface
DoShiftBA, DoExecuteBA, DoHoldBA, ShiftDataToPCAM>BOOL,
ShiftDataToMCtlPads<BOOL
]
Expand
Internal main memory interface
MDataI:INT[32];
MDataDrive, MDataIDrive, MDataPipeBypass, MDataPipeTransfer:BOOL;
MParityI:BOOL;
MCmdIn:EnumType["Dragon.MBusCommands"];
MCmdOutBA:EnumType["Dragon.MBusCommands"];
MCmdDrive:BOOL;
MCmdDriveToDataTransport:BOOL;
MCmdDriveToNoOp:BOOL;
MNSharedSenseBA:BOOL;
MNSharedDriveHigh:BOOL;
MNSharedDriveLow:BOOL;
MNErrorDriveLow:BOOL;
MReadySense:BOOL;
MRqIBA:BOOL;
MNewRqIBA:BOOL;
MNewRqEnableBA:BOOL;
MGntSense:BOOL;
More debug interface
ShiftDataToMRAM, ShiftDataToMCtl, ShiftDataToMCAM:BOOL;
ShiftEqual, nShiftEqual, ShiftFeedBack, nShiftFeedBack, ShiftShift, nShiftShift:BOOL;
MCAMDriver interface
PageAccessToAccess, BlockAccessToAccess:BOOL;
PageVirtualToAccess, BlockVirtualToAccess:BOOL;
MatchToAccess:BOOL;
MDataToMatch, AccessToMatch:BOOL;
PageAccessToMData, nPageAccessToMData:BOOL;
BlockAccessToMData, nBlockAccessToMData:BOOL;
AccessToPageBlockAccess, nAccessToPageBlockAccess, ShiftToPageBlockAccess, nShiftToPageBlockAccess, AccessDrive, nAccessDrive:BOOL;
PageBlockAccessToShift, nPageBlockAccessToShift:BOOL;
nCAMAccessPrecharge:BOOL;
MRAMDriver interface
nMBitsPrecharge, MuxRight, MuxLeft, MBitsDrive, nMBitsDrive, MRamRegToMDataI, nMRamRegToMDataI, SenseMBits, SenseMDataI, ParityIn:BOOL;
ParityOut:BOOL;
SensePBitsLeft, SensePBitsRight, DrivePBits, nDrivePBits:BOOL;
MRamRegToMBits, nMRamRegToMBits:BOOL;
ShiftToMBits, nShiftToMBits, MBitsToShift, nMBitsToShift:BOOL;
mCAMDriver: MCAMDriver[];
mCtl: MCtl[];
mRAMDriver: MRAMDriver[];
mDataPads: MDataPads[];
mCtlPads: MCtlPads[]
ENDCELL