MCtlSequencer:
CELL[
Timing and housekeeping interface
Vdd, Gnd<BOOL,
LatchBias<BOOL,
Buffered timing and housekeeping interface
PhAb, PhBb<BOOL,
PhAh, PhBh<BOOL,
Resetb<BOOL,
Cell control
nVirtualMatch, nMatchPageClean, nMatchCellShared=BOOL,
nMapValid, nRealMatch, nVictimClean=BOOL,
P control <=> M control
MDoneAB, MHeldAB>BOOL,
MFaultAB>EnumType["Dragon.PBusFaults"],
PCmdToMAB<EnumType["Dragon.PBusCommands"],
Debug interface
DoShiftBA, DoExecuteBA, DoHoldBA<BOOL,
Internal main memory interface
MDataI=INT[32],
MDataDrive, MDataIDrive, MDataPipeBypass, MDataPipeTransfer>BOOL,
MCmdIn<EnumType["Dragon.MBusCommands"],
MCmdOutBA>EnumType["Dragon.MBusCommands"],
MCmdDrive>BOOL,
MCmdDriveToDataTransport>BOOL,
MCmdDriveToNoOp>BOOL,
MNSharedSenseBA<BOOL,
MNSharedDriveHigh>BOOL,
MNSharedDriveLow>BOOL,
MNErrorDriveLow>BOOL,
MReadySense<BOOL,
MRqIBA>BOOL,
MNewRqIBA>BOOL,
MNewRqEnableBA>BOOL,
MGntSense<BOOL,
More debug interface
ShiftEqual, nShiftEqual, ShiftFeedBack, nShiftFeedBack, ShiftShift, nShiftShift>BOOL,
MRAMDriver interface
ParityOut<BOOL,
Still more debug interface
ShiftDataToSequencer<BOOL,
ShiftDataToEntryCtl>BOOL,
ShiftExecute, nShiftExecute>BOOL,
CAM control interface
CAMMDataIToMatchReg, CAMGetAdrRefresh, CAMGetAddress, CAMPageAccessToMDataI, CAMLowBitsAccessToMDataI, CAMAccessToMatch, CAMMatchToAccess, CAMVirtualAddressToAccess, CAMDriveCAMAccess>BOOL,
RAM control interface
RAMMDataIToMRAMReg, RAMMBitsToMRAMReg, RAMMRAMRegToMDataI, RAMMRAMRegToMBits, RAMMRAMRegToMBitsNoOrphan, RAMPBitsToMRAMReg, RAMLeftPBitsToMRAMReg, RAMMRAMRegToPBits>BOOL,
Flag control interface
FlagSetShared, FlagRPDirtyVPValid, FlagFlagLatch, FlagResetVPValid, FlagSetFlags, FlagSetTIP, FlagResetTIP, FlagResetMaster>BOOL,
Entry control interface
EntryMDataIToMAdrCtr, EntryGetAddress, EntryGetAdrRefresh, EntryRefresh, EntryMAdrCtrToMAdr, EntryIncMAdrCtr, EntryZeroMAdrCtr, EntryPAdrToMAdrCtr, EntryLowBitsAccessToMDataI, EntryLowBitsZeroToMDataI, EntrySelRealData, EntrySelPageFlag, EntrySelVictimData, EntrySelectVictimOrOrphan, EntryVirtualAccess, EntrynVirtualAccess, EntryShiftVictim, EntryFinishSharedStore>BOOL,
Control steel wool
GetAdrCmdBA>Mnemonic["GetAddressCommands"],
GetAddressDoneBA<BOOL,
LatchSharedAB>BOOL,
IsNoOpBA, IsCleanBA, MatchRealBA>BOOL
]
State
holdTypeBA: BOOL,
notHoldTypeBA: BOOL,
pWantsM: BOOL,
currentPDemandsBA, currentPDemandsAB: BitWord, -- this is actually an array of 7 bools, one per sequence needed.
didRMBA, dirtyPageBA: BOOL,
faultBitsAB: PBusFaults,
mIdleAB, mIdleBA: BOOL,
newRqAB, newRqBA: BOOL,
mGntSenseAB, mRqAB: BOOL,
holdingAB, holdingBA: BOOL,
currentSequenceAB: BitWord,
ioDoneAB: BOOL,
parityErrorAB: BOOL,
cycleShifterAB, cycleShifterBA: BitWord, -- sequence of 7 bits
slaveAB: BOOL,
forceSlaveBA: BOOL,
driveMDataDelayedAB, dCheckParityAB, stopPipeAB: BOOL,
parityBA: BOOL,
mCmdOutAB, mCmdOutBA: MBusCommands,
seqSenseSharedBA, seqMDoneBA, seqDoneBA, seqForceIdleBA, seqForceIdleAB, seqSenseReadyBA, seqMDataIToFaultsBA, seqCheckFaultsBA, seqDriveSharedBA, seqMDataIDriveBA, seqDriveMDataBA, seqDriveMDataDelayedBA, seqDriveMCmdBA, seqDriveMCmdToDataTransportBA, seqDriveMCmdToNoOpBA, seqDCheckParityBA, seqStopPipeNoReadyBA: BOOL,
romSequence: BitWord,
shiftData, nshiftData: BitDWord,
phBLast: BOOL,
pCAMMDataIToMatchReg, pCAMGetAdrRefresh, pCAMGetAddress, pCAMAccessToMatch, pCAMMatchToAccess, pCAMVirtualAddressToAccess, pCAMDriveCAMAccess: BOOL,
pRAMMDataIToMRAMReg, pRAMMBitsToMRAMReg, pRAMMRAMRegToMDataI, pRAMMRAMRegToMBits, pRAMMRAMRegToMBitsNoOrphan, pRAMMRAMRegToPBits: BOOL,
pFlagSetShared, pFlagRPDirtyVPValid, pFlagFlagLatch, pFlagSenseShared, pFlagResetVPValid, pFlagSetFlags, pFlagSetTIP, pFlagResetTIP, pFlagResetMaster:BOOL,
pEntryFinishSharedStore:BOOL
EvalSimple
behaviour[cell];
ENDCELL;
CEDAR
behaviour: CellProc;
RegisterBehaviour:
PUBLIC
PROC[b: CellProc]={
behaviour ← b};