--CacheMCtlRAMCtl.Mesa
--created by RoseTranslate from CacheMCtlRAMCtl.Rose of May 4, 1984 0:03:08 am PDT for Barth.pa at May 4, 1984 0:03:29 am PDT
DIRECTORY
RoseTypes, RoseCreate;
CacheMCtlRAMCtl: CEDAR PROGRAM
IMPORTS RoseCreate =
RegisterCells: PROC =
BEGIN
CreateMCtlRAMCtlPorts[];
[] ← RoseCreate.RegisterCellClass[className: "MCtlRAMCtl",
expandProc: NIL,
ioCreator: CreateMCtlRAMCtlIO, initializer: InitializeMCtlRAMCtl,
evals: [EvalSimple: MCtlRAMCtlEvalSimple],
blackBox: NIL, stateToo: NIL,
ports: MCtlRAMCtlPorts,
drivePrototype: NEW [MCtlRAMCtlDrive]];
END;
CreateMCtlRAMCtlPorts: PROC = {MCtlRAMCtlPorts ← RoseCreate.PortsFromFile["CacheMCtlRAMCtl.MCtlRAMCtl.rosePorts"]};
MCtlRAMCtlIORef: TYPE = REF MCtlRAMCtlIORec;
MCtlRAMCtlIORec: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0..32767],
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0..32767],
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0..32767],
LatchBias(2:15..15): BOOLEAN,
fill3(3:0..14): [0..32767],
PhBb(3:15..15): BOOLEAN,
fill4(4:0..14): [0..32767],
PAdrHigh(4:15..15): BOOLEAN,
fill5(5:0..14): [0..32767],
DoHoldBA(5:15..15): BOOLEAN,
fill6(6:0..14): [0..32767],
ShiftDataToMCtl(6:15..15): BOOLEAN,
fill7(7:0..14): [0..32767],
ShiftEqual(7:15..15): BOOLEAN,
fill8(8:0..14): [0..32767],
nShiftEqual(8:15..15): BOOLEAN,
fill9(9:0..14): [0..32767],
ShiftFeedBack(9:15..15): BOOLEAN,
fill10(10:0..14): [0..32767],
nShiftFeedBack(10:15..15): BOOLEAN,
fill11(11:0..14): [0..32767],
ShiftShift(11:15..15): BOOLEAN,
fill12(12:0..14): [0..32767],
nShiftShift(12:15..15): BOOLEAN,
fill13(13:0..14): [0..32767],
nMBitsPrecharge(13:15..15): BOOLEAN,
fill14(14:0..14): [0..32767],
MuxRight(14:15..15): BOOLEAN,
fill15(15:0..14): [0..32767],
MuxLeft(15:15..15): BOOLEAN,
fill16(16:0..14): [0..32767],
MBitsDrive(16:15..15): BOOLEAN,
fill17(17:0..14): [0..32767],
nMBitsDrive(17:15..15): BOOLEAN,
fill18(18:0..14): [0..32767],
MRamRegToMDataI(18:15..15): BOOLEAN,
fill19(19:0..14): [0..32767],
nMRamRegToMDataI(19:15..15): BOOLEAN,
fill20(20:0..14): [0..32767],
SenseMBits(20:15..15): BOOLEAN,
fill21(21:0..14): [0..32767],
SenseMDataI(21:15..15): BOOLEAN,
fill22(22:0..14): [0..32767],
ParityIn(22:15..15): BOOLEAN,
fill23(23:0..14): [0..32767],
SensePBitsLeft(23:15..15): BOOLEAN,
fill24(24:0..14): [0..32767],
SensePBitsRight(24:15..15): BOOLEAN,
fill25(25:0..14): [0..32767],
DrivePBits(25:15..15): BOOLEAN,
fill26(26:0..14): [0..32767],
nDrivePBits(26:15..15): BOOLEAN,
fill27(27:0..14): [0..32767],
MRamRegToMBits(27:15..15): BOOLEAN,
fill28(28:0..14): [0..32767],
nMRamRegToMBits(28:15..15): BOOLEAN,
fill29(29:0..14): [0..32767],
ShiftToMBits(29:15..15): BOOLEAN,
fill30(30:0..14): [0..32767],
nShiftToMBits(30:15..15): BOOLEAN,
fill31(31:0..14): [0..32767],
MBitsToShift(31:15..15): BOOLEAN,
fill32(32:0..14): [0..32767],
nMBitsToShift(32:15..15): BOOLEAN,
fill33(33:0..14): [0..32767],
ShiftDataToFlagCtl(33:15..15): BOOLEAN,
fill34(34:0..14): [0..32767],
ReadEntry(34:15..15): BOOLEAN,
fill35(35:0..14): [0..32767],
WriteEntry(35:15..15): BOOLEAN,
fill36(36:0..14): [0..32767],
ShiftExecute(36:15..15): BOOLEAN,
fill37(37:0..14): [0..32767],
nShiftExecute(37:15..15): BOOLEAN,
fill38(38:0..14): [0..32767],
RAMMDataIToMRAMReg(38:15..15): BOOLEAN,
fill39(39:0..14): [0..32767],
RAMMBitsToMRAMReg(39:15..15): BOOLEAN,
fill40(40:0..14): [0..32767],
RAMMRAMRegToMDataI(40:15..15): BOOLEAN,
fill41(41:0..14): [0..32767],
RAMMRAMRegToMBits(41:15..15): BOOLEAN,
fill42(42:0..14): [0..32767],
RAMMRAMRegToMBitsNoOrphan(42:15..15): BOOLEAN,
fill43(43:0..14): [0..32767],
RAMPBitsToMRAMReg(43:15..15): BOOLEAN,
fill44(44:0..14): [0..32767],
RAMLeftPBitsToMRAMReg(44:15..15): BOOLEAN,
fill45(45:0..14): [0..32767],
RAMMRAMRegToPBits(45:15..15): BOOLEAN,
fill46(46:0..14): [0..32767],
MatchRealBA(46:15..15): BOOLEAN,
fill47(47:0..14): [0..32767],
MAdrHigh(47:15..15): BOOLEAN];
MCtlRAMCtlDrive: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0 .. 32768),
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0 .. 32768),
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0 .. 32768),
LatchBias(2:15..15): BOOLEAN,
fill3(3:0..14): [0 .. 32768),
PhBb(3:15..15): BOOLEAN,
fill4(4:0..14): [0 .. 32768),
PAdrHigh(4:15..15): BOOLEAN,
fill5(5:0..14): [0 .. 32768),
DoHoldBA(5:15..15): BOOLEAN,
fill6(6:0..14): [0 .. 32768),
ShiftDataToMCtl(6:15..15): BOOLEAN,
fill7(7:0..14): [0 .. 32768),
ShiftEqual(7:15..15): BOOLEAN,
fill8(8:0..14): [0 .. 32768),
nShiftEqual(8:15..15): BOOLEAN,
fill9(9:0..14): [0 .. 32768),
ShiftFeedBack(9:15..15): BOOLEAN,
fill10(10:0..14): [0 .. 32768),
nShiftFeedBack(10:15..15): BOOLEAN,
fill11(11:0..14): [0 .. 32768),
ShiftShift(11:15..15): BOOLEAN,
fill12(12:0..14): [0 .. 32768),
nShiftShift(12:15..15): BOOLEAN,
fill13(13:0..14): [0 .. 32768),
nMBitsPrecharge(13:15..15): BOOLEAN,
fill14(14:0..14): [0 .. 32768),
MuxRight(14:15..15): BOOLEAN,
fill15(15:0..14): [0 .. 32768),
MuxLeft(15:15..15): BOOLEAN,
fill16(16:0..14): [0 .. 32768),
MBitsDrive(16:15..15): BOOLEAN,
fill17(17:0..14): [0 .. 32768),
nMBitsDrive(17:15..15): BOOLEAN,
fill18(18:0..14): [0 .. 32768),
MRamRegToMDataI(18:15..15): BOOLEAN,
fill19(19:0..14): [0 .. 32768),
nMRamRegToMDataI(19:15..15): BOOLEAN,
fill20(20:0..14): [0 .. 32768),
SenseMBits(20:15..15): BOOLEAN,
fill21(21:0..14): [0 .. 32768),
SenseMDataI(21:15..15): BOOLEAN,
fill22(22:0..14): [0 .. 32768),
ParityIn(22:15..15): BOOLEAN,
fill23(23:0..14): [0 .. 32768),
SensePBitsLeft(23:15..15): BOOLEAN,
fill24(24:0..14): [0 .. 32768),
SensePBitsRight(24:15..15): BOOLEAN,
fill25(25:0..14): [0 .. 32768),
DrivePBits(25:15..15): BOOLEAN,
fill26(26:0..14): [0 .. 32768),
nDrivePBits(26:15..15): BOOLEAN,
fill27(27:0..14): [0 .. 32768),
MRamRegToMBits(27:15..15): BOOLEAN,
fill28(28:0..14): [0 .. 32768),
nMRamRegToMBits(28:15..15): BOOLEAN,
fill29(29:0..14): [0 .. 32768),
ShiftToMBits(29:15..15): BOOLEAN,
fill30(30:0..14): [0 .. 32768),
nShiftToMBits(30:15..15): BOOLEAN,
fill31(31:0..14): [0 .. 32768),
MBitsToShift(31:15..15): BOOLEAN,
fill32(32:0..14): [0 .. 32768),
nMBitsToShift(32:15..15): BOOLEAN,
fill33(33:0..14): [0 .. 32768),
ShiftDataToFlagCtl(33:15..15): BOOLEAN,
fill34(34:0..14): [0 .. 32768),
ReadEntry(34:15..15): BOOLEAN,
fill35(35:0..14): [0 .. 32768),
WriteEntry(35:15..15): BOOLEAN,
fill36(36:0..14): [0 .. 32768),
ShiftExecute(36:15..15): BOOLEAN,
fill37(37:0..14): [0 .. 32768),
nShiftExecute(37:15..15): BOOLEAN,
fill38(38:0..14): [0 .. 32768),
RAMMDataIToMRAMReg(38:15..15): BOOLEAN,
fill39(39:0..14): [0 .. 32768),
RAMMBitsToMRAMReg(39:15..15): BOOLEAN,
fill40(40:0..14): [0 .. 32768),
RAMMRAMRegToMDataI(40:15..15): BOOLEAN,
fill41(41:0..14): [0 .. 32768),
RAMMRAMRegToMBits(41:15..15): BOOLEAN,
fill42(42:0..14): [0 .. 32768),
RAMMRAMRegToMBitsNoOrphan(42:15..15): BOOLEAN,
fill43(43:0..14): [0 .. 32768),
RAMPBitsToMRAMReg(43:15..15): BOOLEAN,
fill44(44:0..14): [0 .. 32768),
RAMLeftPBitsToMRAMReg(44:15..15): BOOLEAN,
fill45(45:0..14): [0 .. 32768),
RAMMRAMRegToPBits(45:15..15): BOOLEAN,
fill46(46:0..14): [0 .. 32768),
MatchRealBA(46:15..15): BOOLEAN,
fill47(47:0..14): [0 .. 32768),
MAdrHigh(47:15..15): BOOLEAN];
MCtlRAMCtlStateRef: TYPE = REF MCtlRAMCtlStateRec;
MCtlRAMCtlStateRec: TYPE = RECORD [
shiftHighAddress, nshiftHighAddress: BOOL
];
CreateMCtlRAMCtlIO: IOCreator = {
cell.realCellStuff.newIO ← NEW [MCtlRAMCtlIORec];
cell.realCellStuff.oldIO ← NEW [MCtlRAMCtlIORec];
};
InitializeMCtlRAMCtl: Initializer = {
IF leafily THEN
BEGIN
state: MCtlRAMCtlStateRef ← NEW [MCtlRAMCtlStateRec];
cell.realCellStuff.state ← state;
END;
};
MCtlRAMCtlEvalSimple: CellProc =
BEGIN
newIO: MCtlRAMCtlIORef ← NARROW[cell.realCellStuff.newIO];
state: MCtlRAMCtlStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN newIO, state;
nMBitsPrecharge ← NOT PhBb;
MuxLeft ← IF DoHoldBA THEN shiftHighAddress ELSE NOT MAdrHigh;
MuxRight ← NOT MuxLeft;
MRamRegToMBits ← (RAMMRAMRegToMBits OR (RAMMRAMRegToMBitsNoOrphan AND NOT MatchRealBA));
nMRamRegToMBits ← NOT MRamRegToMBits;
ShiftToMBits ← ShiftExecute AND WriteEntry;
nShiftToMBits ← NOT ShiftToMBits;
MBitsDrive ← MRamRegToMBits OR ShiftToMBits;
nMBitsDrive ← NOT MBitsDrive;
MRamRegToMDataI ← RAMMRAMRegToMDataI;
nMRamRegToMDataI ← NOT MRamRegToMDataI;
SenseMBits ← RAMMBitsToMRAMReg;
SenseMDataI ← RAMMDataIToMRAMReg;
ParityIn ← FALSE;
SensePBitsLeft ← RAMLeftPBitsToMRAMReg OR (RAMPBitsToMRAMReg AND NOT PAdrHigh);
SensePBitsRight ← RAMPBitsToMRAMReg AND PAdrHigh;
DrivePBits ← RAMMRAMRegToPBits;
nDrivePBits ← NOT RAMMRAMRegToPBits;
MBitsToShift ← ShiftExecute AND ReadEntry;
nMBitsToShift ← NOT MBitsToShift;
IF ShiftShift THEN nshiftHighAddress ← NOT ShiftDataToMCtl;
IF ShiftFeedBack THEN nshiftHighAddress ← NOT shiftHighAddress;
IF ShiftEqual THEN shiftHighAddress ← NOT nshiftHighAddress;
ShiftDataToFlagCtl ← shiftHighAddress;
END;
END;
MCtlRAMCtlPorts: Ports ← NEW [PortsRep[48]];
RegisterCells[];
END.