--CacheMCtlFlagCtl.Mesa
--created by RoseTranslate from CacheMCtlFlagCtl.Rose of May 1, 1984 12:44:43 pm PDT for Barth.pa at May 3, 1984 9:26:03 pm PDT
DIRECTORY
RoseTypes, RoseCreate, BitOps, BitSwOps, Dragon, SwitchTypes;
CacheMCtlFlagCtl: CEDAR PROGRAM
IMPORTS RoseCreate, BitOps, BitSwOps, Dragon =
BEGIN OPEN
RoseTypes, BitOps, BitSwOps, Dragon;
RegisterCells: PROC =
BEGIN
CreateMCtlFlagCtlPorts[];
[] ← RoseCreate.RegisterCellClass[className: "MCtlFlagCtl",
expandProc: NIL,
ioCreator: CreateMCtlFlagCtlIO, initializer: InitializeMCtlFlagCtl,
evals: [EvalSimple: MCtlFlagCtlEvalSimple],
blackBox: NIL, stateToo: NIL,
ports: MCtlFlagCtlPorts,
drivePrototype: NEW [MCtlFlagCtlDrive]];
END;
CreateMCtlFlagCtlPorts: PROC = {MCtlFlagCtlPorts ← RoseCreate.PortsFromFile["CacheMCtlFlagCtl.MCtlFlagCtl.rosePorts"]};
MCtlFlagCtlIORef: TYPE = REF MCtlFlagCtlIORec;
MCtlFlagCtlIORec: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0..32767],
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0..32767],
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0..32767],
LatchBias(2:15..15): BOOLEAN,
fill3(3:0..14): [0..32767],
PhAb(3:15..15): BOOLEAN,
fill4(4:0..14): [0..32767],
PhBb(4:15..15): BOOLEAN,
fill5(5:0..14): [0..32767],
Resetb(5:15..15): BOOLEAN,
VPValid(6:0..15): SwitchTypes.SwitchVal,
nVPValid(7:0..15): SwitchTypes.SwitchVal,
RPValid(8:0..15): SwitchTypes.SwitchVal,
nRPValid(9:0..15): SwitchTypes.SwitchVal,
RPDirty(10:0..15): SwitchTypes.SwitchVal,
nRPDirty(11:0..15): SwitchTypes.SwitchVal,
Master(12:0..15): SwitchTypes.SwitchVal,
nMaster(13:0..15): SwitchTypes.SwitchVal,
Shared(14:0..15): SwitchTypes.SwitchVal,
nShared(15:0..15): SwitchTypes.SwitchVal,
Victim(16:0..15): SwitchTypes.SwitchVal,
nVictim(17:0..15): SwitchTypes.SwitchVal,
TIP(18:0..15): SwitchTypes.SwitchVal,
nTIP(19:0..15): SwitchTypes.SwitchVal,
Broken(20:0..15): SwitchTypes.SwitchVal,
nBroken(21:0..15): SwitchTypes.SwitchVal,
MDataI(22:0..31): ARRAY [0..2) OF CARDINAL,
fill23(24:0..14): [0..32767],
ShiftFeedBack(24:15..15): BOOLEAN,
fill24(25:0..14): [0..32767],
nShiftFeedBack(25:15..15): BOOLEAN,
fill25(26:0..14): [0..32767],
ShiftEqual(26:15..15): BOOLEAN,
fill26(27:0..14): [0..32767],
nShiftEqual(27:15..15): BOOLEAN,
fill27(28:0..14): [0..32767],
ShiftShift(28:15..15): BOOLEAN,
fill28(29:0..14): [0..32767],
nShiftShift(29:15..15): BOOLEAN,
fill29(30:0..14): [0..32767],
ShiftDataToFlagCtl(30:15..15): BOOLEAN,
fill30(31:0..14): [0..32767],
ShiftDataToSequencer(31:15..15): BOOLEAN,
fill31(32:0..14): [0..32767],
ReadEntry(32:15..15): BOOLEAN,
fill32(33:0..14): [0..32767],
WriteEntry(33:15..15): BOOLEAN,
fill33(34:0..14): [0..32767],
ShiftExecute(34:15..15): BOOLEAN,
fill34(35:0..14): [0..32767],
nShiftExecute(35:15..15): BOOLEAN,
fill35(36:0..14): [0..32767],
FlagSetShared(36:15..15): BOOLEAN,
fill36(37:0..14): [0..32767],
FlagRPDirtyVPValid(37:15..15): BOOLEAN,
fill37(38:0..14): [0..32767],
FlagFlagLatch(38:15..15): BOOLEAN,
fill38(39:0..14): [0..32767],
FlagResetVPValid(39:15..15): BOOLEAN,
fill39(40:0..14): [0..32767],
FlagSetFlags(40:15..15): BOOLEAN,
fill40(41:0..14): [0..32767],
FlagSetTIP(41:15..15): BOOLEAN,
fill41(42:0..14): [0..32767],
FlagResetTIP(42:15..15): BOOLEAN,
fill42(43:0..14): [0..32767],
IsCleanBA(43:15..15): BOOLEAN,
fill43(44:0..14): [0..32767],
LatchSharedAB(44:15..15): BOOLEAN];
-- port indices:
MCtlFlagCtlVPValidPortIndex: CARDINAL = 6;
MCtlFlagCtlNVPValidPortIndex: CARDINAL = 7;
MCtlFlagCtlRPValidPortIndex: CARDINAL = 8;
MCtlFlagCtlNRPValidPortIndex: CARDINAL = 9;
MCtlFlagCtlRPDirtyPortIndex: CARDINAL = 10;
MCtlFlagCtlNRPDirtyPortIndex: CARDINAL = 11;
MCtlFlagCtlMasterPortIndex: CARDINAL = 12;
MCtlFlagCtlNMasterPortIndex: CARDINAL = 13;
MCtlFlagCtlSharedPortIndex: CARDINAL = 14;
MCtlFlagCtlNSharedPortIndex: CARDINAL = 15;
MCtlFlagCtlVictimPortIndex: CARDINAL = 16;
MCtlFlagCtlNVictimPortIndex: CARDINAL = 17;
MCtlFlagCtlTIPPortIndex: CARDINAL = 18;
MCtlFlagCtlNTIPPortIndex: CARDINAL = 19;
MCtlFlagCtlBrokenPortIndex: CARDINAL = 20;
MCtlFlagCtlNBrokenPortIndex: CARDINAL = 21;
MCtlFlagCtlDrive: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0 .. 32768),
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0 .. 32768),
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0 .. 32768),
LatchBias(2:15..15): BOOLEAN,
fill3(3:0..14): [0 .. 32768),
PhAb(3:15..15): BOOLEAN,
fill4(4:0..14): [0 .. 32768),
PhBb(4:15..15): BOOLEAN,
fill5(5:0..14): [0 .. 32768),
Resetb(5:15..15): BOOLEAN,
fill6(6:0..14): [0 .. 32768),
VPValid(6:15..15): BOOLEAN,
fill7(7:0..14): [0 .. 32768),
nVPValid(7:15..15): BOOLEAN,
fill8(8:0..14): [0 .. 32768),
RPValid(8:15..15): BOOLEAN,
fill9(9:0..14): [0 .. 32768),
nRPValid(9:15..15): BOOLEAN,
fill10(10:0..14): [0 .. 32768),
RPDirty(10:15..15): BOOLEAN,
fill11(11:0..14): [0 .. 32768),
nRPDirty(11:15..15): BOOLEAN,
fill12(12:0..14): [0 .. 32768),
Master(12:15..15): BOOLEAN,
fill13(13:0..14): [0 .. 32768),
nMaster(13:15..15): BOOLEAN,
fill14(14:0..14): [0 .. 32768),
Shared(14:15..15): BOOLEAN,
fill15(15:0..14): [0 .. 32768),
nShared(15:15..15): BOOLEAN,
fill16(16:0..14): [0 .. 32768),
Victim(16:15..15): BOOLEAN,
fill17(17:0..14): [0 .. 32768),
nVictim(17:15..15): BOOLEAN,
fill18(18:0..14): [0 .. 32768),
TIP(18:15..15): BOOLEAN,
fill19(19:0..14): [0 .. 32768),
nTIP(19:15..15): BOOLEAN,
fill20(20:0..14): [0 .. 32768),
Broken(20:15..15): BOOLEAN,
fill21(21:0..14): [0 .. 32768),
nBroken(21:15..15): BOOLEAN,
fill22(22:0..14): [0 .. 32768),
MDataI(22:15..15): BOOLEAN,
fill23(23:0..14): [0 .. 32768),
ShiftFeedBack(23:15..15): BOOLEAN,
fill24(24:0..14): [0 .. 32768),
nShiftFeedBack(24:15..15): BOOLEAN,
fill25(25:0..14): [0 .. 32768),
ShiftEqual(25:15..15): BOOLEAN,
fill26(26:0..14): [0 .. 32768),
nShiftEqual(26:15..15): BOOLEAN,
fill27(27:0..14): [0 .. 32768),
ShiftShift(27:15..15): BOOLEAN,
fill28(28:0..14): [0 .. 32768),
nShiftShift(28:15..15): BOOLEAN,
fill29(29:0..14): [0 .. 32768),
ShiftDataToFlagCtl(29:15..15): BOOLEAN,
fill30(30:0..14): [0 .. 32768),
ShiftDataToSequencer(30:15..15): BOOLEAN,
fill31(31:0..14): [0 .. 32768),
ReadEntry(31:15..15): BOOLEAN,
fill32(32:0..14): [0 .. 32768),
WriteEntry(32:15..15): BOOLEAN,
fill33(33:0..14): [0 .. 32768),
ShiftExecute(33:15..15): BOOLEAN,
fill34(34:0..14): [0 .. 32768),
nShiftExecute(34:15..15): BOOLEAN,
fill35(35:0..14): [0 .. 32768),
FlagSetShared(35:15..15): BOOLEAN,
fill36(36:0..14): [0 .. 32768),
FlagRPDirtyVPValid(36:15..15): BOOLEAN,
fill37(37:0..14): [0 .. 32768),
FlagFlagLatch(37:15..15): BOOLEAN,
fill38(38:0..14): [0 .. 32768),
FlagResetVPValid(38:15..15): BOOLEAN,
fill39(39:0..14): [0 .. 32768),
FlagSetFlags(39:15..15): BOOLEAN,
fill40(40:0..14): [0 .. 32768),
FlagSetTIP(40:15..15): BOOLEAN,
fill41(41:0..14): [0 .. 32768),
FlagResetTIP(41:15..15): BOOLEAN,
fill42(42:0..14): [0 .. 32768),
IsCleanBA(42:15..15): BOOLEAN,
fill43(43:0..14): [0 .. 32768),
LatchSharedAB(43:15..15): BOOLEAN];
MCtlFlagCtlStateRef: TYPE = REF MCtlFlagCtlStateRec;
MCtlFlagCtlStateRec: TYPE = RECORD [
sVPValid, snVPValid, sRPValid, snRPValid, sRPDirty, snRPDirty, sMaster, snMaster, sShared, snShared, sVictim, snVictim, sTIP, snTIP, sBroken, snBroken: BOOL,
vPValidBit, rPDirtyBit: BOOL
];
CreateMCtlFlagCtlIO: IOCreator = {
cell.realCellStuff.switchIO ← NEW [MCtlFlagCtlIORec];
cell.realCellStuff.newIO ← NEW [MCtlFlagCtlIORec];
cell.realCellStuff.oldIO ← NEW [MCtlFlagCtlIORec];
};
InitializeMCtlFlagCtl: Initializer = {
IF leafily THEN
BEGIN
state: MCtlFlagCtlStateRef ← NEW [MCtlFlagCtlStateRec];
cell.realCellStuff.state ← state;
END;
};
MCtlFlagCtlEvalSimple: CellProc =
BEGIN
sw: MCtlFlagCtlIORef ← NARROW[cell.realCellStuff.switchIO];
newIO: MCtlFlagCtlIORef ← NARROW[cell.realCellStuff.newIO];
state: MCtlFlagCtlStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN newIO, state;
DriveBit: PROC[bit, nBit: Switch, dBit: BOOL] RETURNS [newBit, newNBit: Switch] = {
newBit ← SIBISS[dBit, bit, [[driveStrong, L], [driveStrong, H]]];
newNBit ← SIBISS[dBit, nBit, [[driveStrong, H], [driveStrong, L]]];
};
Assert[NOT MoreThanOneOf[ShiftFeedBack, ShiftShift]];
Assert[NOT MoreThanOneOf[ShiftFeedBack, ShiftEqual]];
Assert[NOT MoreThanOneOf[ShiftEqual, ShiftShift]];
Assert[NOT MoreThanOneOf[ShiftFeedBack, nShiftFeedBack]];
Assert[NOT MoreThanOneOf[ShiftEqual, nShiftEqual]];
Assert[NOT MoreThanOneOf[ShiftShift, nShiftShift]];
{
s: SwitchTypes.Strength ← IF PhBb THEN drive ELSE none;
VPValid ← SIBISS[TRUE, VPValid, [[none, X], [s, H]]];
nVPValid ← SIBISS[TRUE, nVPValid, [[none, X], [s, H]]];
RPValid ← SIBISS[TRUE, RPValid, [[none, X], [s, H]]];
nRPValid ← SIBISS[TRUE, nRPValid, [[none, X], [s, H]]];
RPDirty ← SIBISS[TRUE, RPDirty, [[none, X], [s, H]]];
nRPDirty ← SIBISS[TRUE, nRPDirty, [[none, X], [s, H]]];
Master ← SIBISS[TRUE, Master, [[none, X], [s, H]]];
nMaster ← SIBISS[TRUE, nMaster, [[none, X], [s, H]]];
Shared ← SIBISS[TRUE, Shared, [[none, X], [s, H]]];
nShared ← SIBISS[TRUE, nShared, [[none, X], [s, H]]];
Victim ← SIBISS[TRUE, Victim, [[none, X], [s, H]]];
nVictim ← SIBISS[TRUE, nVictim, [[none, X], [s, H]]];
TIP ← SIBISS[TRUE, TIP, [[none, X], [s, H]]];
nTIP ← SIBISS[TRUE, nTIP, [[none, X], [s, H]]];
Broken ← SIBISS[TRUE, Broken, [[none, X], [s, H]]];
nBroken ← SIBISS[TRUE, nBroken, [[none, X], [s, H]]];
};
--The next block of code assumes that the instructions have been set to none and only sets the instructions if a strength other than none is to be applied.
--
IF Resetb AND PhAb THEN {
[VPValid, nVPValid] ← DriveBit[VPValid, nVPValid, FALSE];
[RPValid, nRPValid] ← DriveBit[RPValid, nRPValid, FALSE];
[RPDirty, nRPDirty] ← DriveBit[RPDirty, nRPDirty, FALSE];
[Master, nMaster] ← DriveBit[Master, nMaster, FALSE];
[Shared, nShared] ← DriveBit[Shared, nShared, FALSE];
[Victim, nVictim] ← DriveBit[Victim, nVictim, FALSE];
[TIP, nTIP] ← DriveBit[TIP, nTIP, FALSE];
[Broken, nBroken] ← DriveBit[Broken, nBroken, FALSE];
};
IF FlagSetShared THEN [Shared, nShared] ← DriveBit[Shared, nShared, TRUE];
IF FlagRPDirtyVPValid THEN {
[VPValid, nVPValid] ← DriveBit[VPValid, nVPValid, vPValidBit];
[RPDirty, nRPDirty] ← DriveBit[RPDirty, nRPDirty, rPDirtyBit];
};
IF FlagFlagLatch THEN {
vPValidBit ← EBFD[MDataI, 32, 30];
rPDirtyBit ← EBFD[MDataI, 32, 31];
};
IF FlagResetVPValid THEN [VPValid, nVPValid] ← DriveBit[VPValid, nVPValid, FALSE];
IF FlagSetFlags THEN {
[VPValid, nVPValid] ← DriveBit[VPValid, nVPValid, TRUE];
[RPValid, nRPValid] ← DriveBit[RPValid, nRPValid, TRUE];
[RPDirty, nRPDirty] ← DriveBit[RPDirty, nRPDirty, NOT IsCleanBA];
[Master, nMaster] ← DriveBit[Master, nMaster, FALSE];
[Shared, nShared] ← DriveBit[Shared, nShared, LatchSharedAB];
[TIP, nTIP] ← DriveBit[TIP, nTIP, FALSE];
};
IF FlagSetTIP THEN [TIP, nTIP] ← DriveBit[TIP, nTIP, TRUE];
IF FlagResetTIP THEN [TIP, nTIP] ← DriveBit[TIP, nTIP, FALSE];
IF ShiftExecute AND WriteEntry THEN {
[VPValid, nVPValid] ← DriveBit[VPValid, nVPValid, sVPValid];
[RPValid, nRPValid] ← DriveBit[RPValid, nRPValid, sRPValid];
[RPDirty, nRPDirty] ← DriveBit[RPDirty, nRPDirty, sRPDirty];
[Master, nMaster] ← DriveBit[Master, nMaster, sMaster];
[Shared, nShared] ← DriveBit[Shared, nShared, sShared];
[Victim, nVictim] ← DriveBit[Victim, nVictim, sVictim];
[TIP, nTIP] ← DriveBit[TIP, nTIP, sTIP];
[Broken, nBroken] ← DriveBit[Broken, nBroken, sBroken];
};
IF ShiftExecute AND ReadEntry THEN {
snVPValid ← NOT EBFSS[VPValid];
snRPValid ← NOT EBFSS[RPValid];
snRPDirty ← NOT EBFSS[RPDirty];
snMaster ← NOT EBFSS[Master];
snShared ← NOT EBFSS[Shared];
snVictim ← NOT EBFSS[Victim];
snTIP ← NOT EBFSS[TIP];
snBroken ← NOT EBFSS[Broken];
};
IF ShiftShift THEN {
snVPValid ← NOT ShiftDataToFlagCtl;
snRPValid ← NOT sVPValid;
snRPDirty ← NOT sRPValid;
snMaster ← NOT sRPDirty;
snShared ← NOT sMaster;
snVictim ← NOT sShared;
snTIP ← NOT sVictim;
snBroken ← NOT sTIP;
};
IF ShiftFeedBack THEN {
snVPValid ← NOT sVPValid;
snRPValid ← NOT sRPValid;
snRPDirty ← NOT sRPDirty;
snMaster ← NOT sMaster;
snShared ← NOT sMaster;
snVictim ← NOT sVictim;
snTIP ← NOT sTIP;
snBroken ← NOT sBroken;
};
IF ShiftEqual THEN {
sVPValid ← NOT snVPValid;
sRPValid ← NOT snRPValid;
sRPDirty ← NOT snRPDirty;
sMaster ← NOT snMaster;
sShared ← NOT snShared;
sVictim ← NOT snVictim;
sTIP ← NOT snTIP;
sBroken ← NOT snBroken;
ShiftDataToSequencer ← sBroken;
};
--
END;
END;
MCtlFlagCtlPorts: Ports ← NEW [PortsRep[44]];
RegisterCells[];
END.