Library CacheMCtlSequencer, CacheMCtlEntryCtl, CacheMCtlFlagCtl, CacheMCtlRAMCtl, CacheMCtlCAMCtl;
MCtl:
CELL[
Timing and housekeeping interface
Vdd, Gnd<BOOL,
LatchBias<BOOL,
Buffered timing and housekeeping interface
PhAb, PhBb<BOOL,
PhAh, PhBh<BOOL,
Resetb<BOOL,
Cell control
nVirtualMatch, nMatchPageClean, nMatchCellShared=BOOL,
nMapValid, nRealMatch, nVictimClean=BOOL,
CellAdr, nCellAdr>INT[8],
VirtualAccess, nVirtualAccess, SelCell, SelVictimAdr, SelMapAdr, SelRealData, SelPageFlag, SelVictimData, SelRealAdr>BOOL,
FinishSharedStore>BOOL,
VPValid, nVPValid, RPValid, nRPValid, RPDirty, nRPDirty, Master, nMaster, Shared, nShared, Victim, nVictim, TIP, nTIP, Broken, nBroken=BIT,
MAdrLow, nMAdrLow>BOOL,
VictimFeedback, nVictimFeedback, ShiftVictim, nShiftVictim>BOOL,
ForceDataSelect>BOOL,
P control <=> M control
MDoneAB, MHeldAB>BOOL,
MFaultAB>EnumType["Dragon.PBusFaults"],
PAdrHigh, PAdrLowToM<BOOL,
PCmdToMAB<EnumType["Dragon.PBusCommands"],
Debug interface
DoShiftBA, DoExecuteBA, DoHoldBA<BOOL,
Internal main memory interface
MDataI=INT[32],
MDataDrive, MDataIDrive, MDataPipeBypass, MDataPipeTransfer>BOOL,
MCmdIn<EnumType["Dragon.MBusCommands"],
MCmdOutBA>EnumType["Dragon.MBusCommands"],
MCmdDrive>BOOL,
MCmdDriveToDataTransport>BOOL,
MCmdDriveToNoOp>BOOL,
MNSharedSenseBA<BOOL,
MNSharedDriveHigh>BOOL,
MNSharedDriveLow>BOOL,
MNErrorDriveLow>BOOL,
MReadySense<BOOL,
MRqIBA>BOOL,
MNewRqIBA>BOOL,
MNewRqEnableBA>BOOL,
MGntSense<BOOL,
More debug interface
ShiftDataToMCtl<BOOL,
ShiftDataToMCAM>BOOL,
ShiftEqual, nShiftEqual, ShiftFeedBack, nShiftFeedBack, ShiftShift, nShiftShift>BOOL,
MCAMDriver interface
PageAccessToAccess, BlockAccessToAccess>BOOL,
PageVirtualToAccess, BlockVirtualToAccess>BOOL,
MatchToAccess>BOOL,
MDataToMatch, AccessToMatch>BOOL,
PageAccessToMData, nPageAccessToMData>BOOL,
BlockAccessToMData, nBlockAccessToMData>BOOL,
AccessToPageBlockAccess, nAccessToPageBlockAccess, ShiftToPageBlockAccess, nShiftToPageBlockAccess, AccessDrive, nAccessDrive>BOOL,
PageBlockAccessToShift, nPageBlockAccessToShift>BOOL,
nCAMAccessPrecharge>BOOL,
MRAMDriver interface
nMBitsPrecharge, MuxRight, MuxLeft, MBitsDrive, nMBitsDrive, MRamRegToMDataI, nMRamRegToMDataI, SenseMBits, SenseMDataI, ParityIn>BOOL,
ParityOut<BOOL,
SensePBitsLeft, SensePBitsRight, DrivePBits, nDrivePBits>BOOL,
MRamRegToMBits, nMRamRegToMBits>BOOL,
ShiftToMBits, nShiftToMBits, MBitsToShift, nMBitsToShift>BOOL
]
Expand
Still more debug interface
ShiftDataToFlagCtl, ShiftDataToSequencer, ShiftDataToEntryCtl, ShiftDataToCAMCtl: BOOL;
ShiftExecute, nShiftExecute: BOOL;
ReadEntry, WriteEntry: BOOL;
CAM control interface
CAMMDataIToMatchReg, CAMGetAdrRefresh, CAMGetAddress, CAMPageAccessToMDataI, CAMLowBitsAccessToMDataI, CAMAccessToMatch, CAMMatchToAccess, CAMVirtualAddressToAccess, CAMDriveCAMAccess: BOOL;
RAM control interface
RAMMDataIToMRAMReg, RAMMBitsToMRAMReg, RAMMRAMRegToMDataI, RAMMRAMRegToMBits, RAMMRAMRegToMBitsNoOrphan, RAMPBitsToMRAMReg, RAMLeftPBitsToMRAMReg, RAMMRAMRegToPBits: BOOL;
Flag control interface
FlagSetShared, FlagRPDirtyVPValid, FlagFlagLatch, FlagResetVPValid, FlagSetFlags, FlagSetTIP, FlagResetTIP, FlagResetMaster: BOOL;
Entry control interface
EntryMDataIToMAdrCtr, EntryGetAddress, EntryGetAdrRefresh, EntryRefresh, EntryMAdrCtrToMAdr, EntryIncMAdrCtr, EntryZeroMAdrCtr, EntryPAdrToMAdrCtr, EntryLowBitsAccessToMDataI, EntryLowBitsZeroToMDataI, EntrySelRealData, EntrySelPageFlag, EntrySelVictimData, EntrySelectVictimOrOrphan, EntryVirtualAccess, EntrynVirtualAccess, EntryShiftVictim, EntryFinishSharedStore: BOOL;
Control steel wool
GetAdrCmdBA: Mnemonic["GetAddressCommands"];
GetAddressDoneBA: BOOL;
LatchSharedAB: BOOL;
IsNoOpBA, IsCleanBA, MatchRealBA: BOOL;
MAdrHigh: BOOL;
mCtlSequencer:MCtlSequencer[];
mCtlEntryCtl:MCtlEntryCtl[];
mCtlFlagCtl:MCtlFlagCtl[];
mCtlRAMCtl:MCtlRAMCtl[];
mCtlCAMCtl:MCtlCAMCtl[]
ENDCELL