--CacheEntry.Mesa
--created by RoseTranslate from CacheEntry.Rose of May 22, 1984 8:16:57 pm PDT for Barth.pa at May 22, 1984 8:27:59 pm PDT
DIRECTORY
RoseTypes, RoseCreate, BitOps, BitSwOps, Dragon, SwitchTypes;
CacheEntry: CEDAR PROGRAM
IMPORTS RoseCreate, BitOps, BitSwOps, Dragon =
BEGIN OPEN
RoseTypes, BitOps, BitSwOps, Dragon;
RegisterCells: PROC =
BEGIN
CreateCacheEntryPorts[];
[] ← RoseCreate.RegisterCellClass[className: "CacheEntry",
expandProc: NIL,
ioCreator: CreateCacheEntryIO, initializer: InitializeCacheEntry,
evals: [EvalSimple: CacheEntryEvalSimple],
blackBox: NIL, stateToo: NIL,
ports: CacheEntryPorts,
drivePrototype: NEW [CacheEntryDrive]];
END;
--explicitly requested CEDAR:
memBits: TYPE = ARRAY [0..5) OF BitWord;
CreateCacheEntryPorts: PROC = {CacheEntryPorts ← RoseCreate.PortsFromFile["CacheEntry.CacheEntry.rosePorts"]};
CacheEntryIORef: TYPE = REF CacheEntryIORec;
CacheEntryIORec: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0..32767],
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0..32767],
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0..32767],
PhAb(2:15..15): BOOLEAN,
fill3(3:0..14): [0..32767],
PhBb(3:15..15): BOOLEAN,
fill4(4:0..14): [0..32767],
nPhBb(4:15..15): BOOLEAN,
fill5(5:0..14): [0..32767],
Resetb(5:15..15): BOOLEAN,
VirtualPage(6:0..31): ARRAY [0..2) OF CARDINAL,
nVirtualPage(8:0..31): ARRAY [0..2) OF CARDINAL,
fill8(10:0..9): [0..1023],
VirtualBlock(10:10..15): [0..63],
fill9(11:0..9): [0..1023],
nVirtualBlock(11:10..15): [0..63],
RealPage(12:0..31): ARRAY [0..2) OF CARDINAL,
nRealPage(14:0..31): ARRAY [0..2) OF CARDINAL,
fill12(16:0..9): [0..1023],
RealBlock(16:10..15): [0..63],
fill13(17:0..9): [0..1023],
nRealBlock(17:10..15): [0..63],
CAMPageAccess(18:0..383): PACKED ARRAY [0 .. 23] OF SwitchTypes.SwitchVal,
nCAMPageAccess(42:0..383): PACKED ARRAY [0 .. 23] OF SwitchTypes.SwitchVal,
CAMBlockAccess(66:0..95): PACKED ARRAY [0 .. 5] OF SwitchTypes.SwitchVal,
nCAMBlockAccess(72:0..95): PACKED ARRAY [0 .. 5] OF SwitchTypes.SwitchVal,
PBits(78:0..1055): PACKED ARRAY [0 .. 65] OF SwitchTypes.SwitchVal,
nPBits(144:0..1055): PACKED ARRAY [0 .. 65] OF SwitchTypes.SwitchVal,
MBits(210:0..1055): PACKED ARRAY [0 .. 65] OF SwitchTypes.SwitchVal,
nMBits(276:0..1055): PACKED ARRAY [0 .. 65] OF SwitchTypes.SwitchVal,
fill22(342:0..14): [0..32767],
nVirtualMatch(342:15..15): BOOLEAN,
fill23(343:0..14): [0..32767],
nMatchPageClean(343:15..15): BOOLEAN,
fill24(344:0..14): [0..32767],
nMatchCellShared(344:15..15): BOOLEAN,
fill25(345:0..14): [0..32767],
nMapValid(345:15..15): BOOLEAN,
fill26(346:0..14): [0..32767],
nRealMatch(346:15..15): BOOLEAN,
fill27(347:0..14): [0..32767],
nVictimClean(347:15..15): BOOLEAN,
fill28(348:0..14): [0..32767],
nMatchTIP(348:15..15): BOOLEAN,
fill29(349:0..7): [0..255],
CellAdr(349:8..15): [0..255],
fill30(350:0..7): [0..255],
nCellAdr(350:8..15): [0..255],
fill31(351:0..14): [0..32767],
VirtualAccess(351:15..15): BOOLEAN,
fill32(352:0..14): [0..32767],
nVirtualAccess(352:15..15): BOOLEAN,
fill33(353:0..14): [0..32767],
SelCell(353:15..15): BOOLEAN,
fill34(354:0..14): [0..32767],
SelVictimAdr(354:15..15): BOOLEAN,
fill35(355:0..14): [0..32767],
SelMapAdr(355:15..15): BOOLEAN,
fill36(356:0..14): [0..32767],
SelRealData(356:15..15): BOOLEAN,
fill37(357:0..14): [0..32767],
SelPageFlag(357:15..15): BOOLEAN,
fill38(358:0..14): [0..32767],
SelVictimData(358:15..15): BOOLEAN,
fill39(359:0..14): [0..32767],
SelRealAdr(359:15..15): BOOLEAN,
fill40(360:0..14): [0..32767],
FinishSharedStore(360:15..15): BOOLEAN,
VPValid(361:0..15): SwitchTypes.SwitchVal,
nVPValid(362:0..15): SwitchTypes.SwitchVal,
RPValid(363:0..15): SwitchTypes.SwitchVal,
nRPValid(364:0..15): SwitchTypes.SwitchVal,
RPDirty(365:0..15): SwitchTypes.SwitchVal,
nRPDirty(366:0..15): SwitchTypes.SwitchVal,
Master(367:0..15): SwitchTypes.SwitchVal,
nMaster(368:0..15): SwitchTypes.SwitchVal,
Shared(369:0..15): SwitchTypes.SwitchVal,
nShared(370:0..15): SwitchTypes.SwitchVal,
Victim(371:0..15): SwitchTypes.SwitchVal,
nVictim(372:0..15): SwitchTypes.SwitchVal,
TIP(373:0..15): SwitchTypes.SwitchVal,
nTIP(374:0..15): SwitchTypes.SwitchVal,
Broken(375:0..15): SwitchTypes.SwitchVal,
nBroken(376:0..15): SwitchTypes.SwitchVal,
fill57(377:0..14): [0..32767],
MAdrLow(377:15..15): BOOLEAN,
fill58(378:0..14): [0..32767],
nMAdrLow(378:15..15): BOOLEAN,
fill59(379:0..14): [0..32767],
PAdrLow(379:15..15): BOOLEAN,
fill60(380:0..14): [0..32767],
nPAdrLow(380:15..15): BOOLEAN,
fill61(381:0..14): [0..32767],
PStore(381:15..15): BOOLEAN,
fill62(382:0..14): [0..32767],
VictimFeedback(382:15..15): BOOLEAN,
fill63(383:0..14): [0..32767],
nVictimFeedback(383:15..15): BOOLEAN,
fill64(384:0..14): [0..32767],
ShiftVictim(384:15..15): BOOLEAN,
fill65(385:0..14): [0..32767],
nShiftVictim(385:15..15): BOOLEAN,
fill66(386:0..14): [0..32767],
ForceDataSelect(386:15..15): BOOLEAN,
fill67(387:0..14): [0..32767],
VictimIn(387:15..15): BOOLEAN,
fill68(388:0..14): [0..32767],
VictimOut(388:15..15): BOOLEAN];
-- port indices:
CacheEntryCAMPageAccessPortIndex: CARDINAL = 14;
CacheEntryNCAMPageAccessPortIndex: CARDINAL = 15;
CacheEntryCAMBlockAccessPortIndex: CARDINAL = 16;
CacheEntryNCAMBlockAccessPortIndex: CARDINAL = 17;
CacheEntryPBitsPortIndex: CARDINAL = 18;
CacheEntryNPBitsPortIndex: CARDINAL = 19;
CacheEntryMBitsPortIndex: CARDINAL = 20;
CacheEntryNMBitsPortIndex: CARDINAL = 21;
CacheEntryVPValidPortIndex: CARDINAL = 41;
CacheEntryNVPValidPortIndex: CARDINAL = 42;
CacheEntryRPValidPortIndex: CARDINAL = 43;
CacheEntryNRPValidPortIndex: CARDINAL = 44;
CacheEntryRPDirtyPortIndex: CARDINAL = 45;
CacheEntryNRPDirtyPortIndex: CARDINAL = 46;
CacheEntryMasterPortIndex: CARDINAL = 47;
CacheEntryNMasterPortIndex: CARDINAL = 48;
CacheEntrySharedPortIndex: CARDINAL = 49;
CacheEntryNSharedPortIndex: CARDINAL = 50;
CacheEntryVictimPortIndex: CARDINAL = 51;
CacheEntryNVictimPortIndex: CARDINAL = 52;
CacheEntryTIPPortIndex: CARDINAL = 53;
CacheEntryNTIPPortIndex: CARDINAL = 54;
CacheEntryBrokenPortIndex: CARDINAL = 55;
CacheEntryNBrokenPortIndex: CARDINAL = 56;
CacheEntryDrive: TYPE = MACHINE DEPENDENT RECORD [
fill0(0:0..14): [0 .. 32768),
Vdd(0:15..15): BOOLEAN,
fill1(1:0..14): [0 .. 32768),
Gnd(1:15..15): BOOLEAN,
fill2(2:0..14): [0 .. 32768),
PhAb(2:15..15): BOOLEAN,
fill3(3:0..14): [0 .. 32768),
PhBb(3:15..15): BOOLEAN,
fill4(4:0..14): [0 .. 32768),
nPhBb(4:15..15): BOOLEAN,
fill5(5:0..14): [0 .. 32768),
Resetb(5:15..15): BOOLEAN,
fill6(6:0..14): [0 .. 32768),
VirtualPage(6:15..15): BOOLEAN,
fill7(7:0..14): [0 .. 32768),
nVirtualPage(7:15..15): BOOLEAN,
fill8(8:0..14): [0 .. 32768),
VirtualBlock(8:15..15): BOOLEAN,
fill9(9:0..14): [0 .. 32768),
nVirtualBlock(9:15..15): BOOLEAN,
fill10(10:0..14): [0 .. 32768),
RealPage(10:15..15): BOOLEAN,
fill11(11:0..14): [0 .. 32768),
nRealPage(11:15..15): BOOLEAN,
fill12(12:0..14): [0 .. 32768),
RealBlock(12:15..15): BOOLEAN,
fill13(13:0..14): [0 .. 32768),
nRealBlock(13:15..15): BOOLEAN,
fill14(14:0..14): [0 .. 32768),
CAMPageAccess(14:15..15): BOOLEAN,
fill15(15:0..14): [0 .. 32768),
nCAMPageAccess(15:15..15): BOOLEAN,
fill16(16:0..14): [0 .. 32768),
CAMBlockAccess(16:15..15): BOOLEAN,
fill17(17:0..14): [0 .. 32768),
nCAMBlockAccess(17:15..15): BOOLEAN,
fill18(18:0..14): [0 .. 32768),
PBits(18:15..15): BOOLEAN,
fill19(19:0..14): [0 .. 32768),
nPBits(19:15..15): BOOLEAN,
fill20(20:0..14): [0 .. 32768),
MBits(20:15..15): BOOLEAN,
fill21(21:0..14): [0 .. 32768),
nMBits(21:15..15): BOOLEAN,
fill22(22:0..14): [0 .. 32768),
nVirtualMatch(22:15..15): BOOLEAN,
fill23(23:0..14): [0 .. 32768),
nMatchPageClean(23:15..15): BOOLEAN,
fill24(24:0..14): [0 .. 32768),
nMatchCellShared(24:15..15): BOOLEAN,
fill25(25:0..14): [0 .. 32768),
nMapValid(25:15..15): BOOLEAN,
fill26(26:0..14): [0 .. 32768),
nRealMatch(26:15..15): BOOLEAN,
fill27(27:0..14): [0 .. 32768),
nVictimClean(27:15..15): BOOLEAN,
fill28(28:0..14): [0 .. 32768),
nMatchTIP(28:15..15): BOOLEAN,
fill29(29:0..14): [0 .. 32768),
CellAdr(29:15..15): BOOLEAN,
fill30(30:0..14): [0 .. 32768),
nCellAdr(30:15..15): BOOLEAN,
fill31(31:0..14): [0 .. 32768),
VirtualAccess(31:15..15): BOOLEAN,
fill32(32:0..14): [0 .. 32768),
nVirtualAccess(32:15..15): BOOLEAN,
fill33(33:0..14): [0 .. 32768),
SelCell(33:15..15): BOOLEAN,
fill34(34:0..14): [0 .. 32768),
SelVictimAdr(34:15..15): BOOLEAN,
fill35(35:0..14): [0 .. 32768),
SelMapAdr(35:15..15): BOOLEAN,
fill36(36:0..14): [0 .. 32768),
SelRealData(36:15..15): BOOLEAN,
fill37(37:0..14): [0 .. 32768),
SelPageFlag(37:15..15): BOOLEAN,
fill38(38:0..14): [0 .. 32768),
SelVictimData(38:15..15): BOOLEAN,
fill39(39:0..14): [0 .. 32768),
SelRealAdr(39:15..15): BOOLEAN,
fill40(40:0..14): [0 .. 32768),
FinishSharedStore(40:15..15): BOOLEAN,
fill41(41:0..14): [0 .. 32768),
VPValid(41:15..15): BOOLEAN,
fill42(42:0..14): [0 .. 32768),
nVPValid(42:15..15): BOOLEAN,
fill43(43:0..14): [0 .. 32768),
RPValid(43:15..15): BOOLEAN,
fill44(44:0..14): [0 .. 32768),
nRPValid(44:15..15): BOOLEAN,
fill45(45:0..14): [0 .. 32768),
RPDirty(45:15..15): BOOLEAN,
fill46(46:0..14): [0 .. 32768),
nRPDirty(46:15..15): BOOLEAN,
fill47(47:0..14): [0 .. 32768),
Master(47:15..15): BOOLEAN,
fill48(48:0..14): [0 .. 32768),
nMaster(48:15..15): BOOLEAN,
fill49(49:0..14): [0 .. 32768),
Shared(49:15..15): BOOLEAN,
fill50(50:0..14): [0 .. 32768),
nShared(50:15..15): BOOLEAN,
fill51(51:0..14): [0 .. 32768),
Victim(51:15..15): BOOLEAN,
fill52(52:0..14): [0 .. 32768),
nVictim(52:15..15): BOOLEAN,
fill53(53:0..14): [0 .. 32768),
TIP(53:15..15): BOOLEAN,
fill54(54:0..14): [0 .. 32768),
nTIP(54:15..15): BOOLEAN,
fill55(55:0..14): [0 .. 32768),
Broken(55:15..15): BOOLEAN,
fill56(56:0..14): [0 .. 32768),
nBroken(56:15..15): BOOLEAN,
fill57(57:0..14): [0 .. 32768),
MAdrLow(57:15..15): BOOLEAN,
fill58(58:0..14): [0 .. 32768),
nMAdrLow(58:15..15): BOOLEAN,
fill59(59:0..14): [0 .. 32768),
PAdrLow(59:15..15): BOOLEAN,
fill60(60:0..14): [0 .. 32768),
nPAdrLow(60:15..15): BOOLEAN,
fill61(61:0..14): [0 .. 32768),
PStore(61:15..15): BOOLEAN,
fill62(62:0..14): [0 .. 32768),
VictimFeedback(62:15..15): BOOLEAN,
fill63(63:0..14): [0 .. 32768),
nVictimFeedback(63:15..15): BOOLEAN,
fill64(64:0..14): [0 .. 32768),
ShiftVictim(64:15..15): BOOLEAN,
fill65(65:0..14): [0 .. 32768),
nShiftVictim(65:15..15): BOOLEAN,
fill66(66:0..14): [0 .. 32768),
ForceDataSelect(66:15..15): BOOLEAN,
fill67(67:0..14): [0 .. 32768),
VictimIn(67:15..15): BOOLEAN,
fill68(68:0..14): [0 .. 32768),
VictimOut(68:15..15): BOOLEAN];
CacheEntryInitRef: TYPE = REF CacheEntryInitRec;
CacheEntryInitRec: PUBLIC TYPE = RECORD [
cellNumber: BitWord
];
CacheEntryStateRef: TYPE = REF CacheEntryStateRec;
CacheEntryStateRec: TYPE = RECORD [
vpValid, nvpValid: BOOL,
rpValid, nrpValid: BOOL,
rpDirty, nrpDirty: BOOL,
master, nmaster: BOOL,
shared, nshared: BOOL,
victim, nvictim: BOOL,
tip, ntip: BOOL,
broken, nbroken: BOOL,
hexVirtualPage, hexRealPage, hexBlock: HexWord,
words: ARRAY [0..4) OF HexWord,
parity: ARRAY [0..4) OF BOOL,
virtualPage, nvirtualPage: BitDWord,
realPage, nrealPage: BitDWord,
block, nblock: BitWord,
data: ARRAY [0..2) OF ARRAY BOOLEAN OF memBits,
vpMatch, vblMatch, rpMatch, rblMatch: BOOL,
selVMap, vSelCell, selRMap, rSelCell: BOOL,
decodeSelect, victimAdrSelect, victimDataSelect, victimFlagSelect: BOOL,
realMatchSelect, dataSelect, addressSelect, virtualDataSelect: BOOL,
thisCellAdr: BitWord
];
CreateCacheEntryIO: IOCreator = {
cell.realCellStuff.switchIO ← NEW [CacheEntryIORec];
cell.realCellStuff.newIO ← NEW [CacheEntryIORec];
cell.realCellStuff.oldIO ← NEW [CacheEntryIORec];
};
InitializeCacheEntry: Initializer = {
IF leafily THEN
BEGIN
ioRec: CacheEntryIORef ← NARROW[cell.realCellStuff.newIO];
narrowedInitData: CacheEntryInitRef ← NARROW[initData];
state: CacheEntryStateRef ← NEW [CacheEntryStateRec];
cell.realCellStuff.state ← state;
BEGIN OPEN ioRec, narrowedInitData, state;
thisCellAdr ← cellNumber;
END;
END;
};
CacheEntryEvalSimple: CellProc =
BEGIN
sw: CacheEntryIORef ← NARROW[cell.realCellStuff.switchIO];
newIO: CacheEntryIORef ← NARROW[cell.realCellStuff.newIO];
state: CacheEntryStateRef ← NARROW[cell.realCellStuff.state];
BEGIN OPEN newIO, state;
oldMemBits: ARRAY [0..2) OF memBits;
RWB: PROC [access: BOOL, bus, nBus: Switch, bit, nbit: BOOL] RETURNS [newBus, nNewBus: Switch, newBit, newnBit: BOOL] = {
s: SwitchTypes.Strength ← IF access THEN drive ELSE none;
IF access THEN {
bit ← (NOT nbit) AND bus.val=H;
nbit ← (NOT bit) AND nBus.val=H;
bit ← (NOT nbit) AND bus.val=H;
};
nNewBus ← SIBISS[bit, nBus, [[none, X], [s, L]]];
newBus ← SIBISS[nbit, bus, [[none, X], [s, L]]];
newBit ← bit;
newnBit ← nbit;
};
RWW: PROC [access: BOOL, busD, nBusD: SwitchMWord, field, nfield: BitWord, fieldWidth: CARDINAL] RETURNS [newField, newnField: BitWord] = TRUSTED {
s: SwitchTypes.Strength ← IF access THEN drive ELSE none;
IF access THEN FOR i:CARDINAL IN [0..fieldWidth) DO
field ← IBIW[(NOT EBFW[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
nfield ← IBIW[(NOT EBFW[field, fieldWidth, i]) AND nBusD[i].val=H, nfield, fieldWidth, i];
field ← IBIW[(NOT EBFW[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
ENDLOOP;
SCWTS[field, fieldWidth, 0, fieldWidth, nBusD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
SCWTS[nfield, fieldWidth, 0, fieldWidth, busD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
newField ← field;
newnField ← nfield;
};
RWD: PROC [access: BOOL, busD, nBusD: SwitchMWord, field, nfield: BitDWord, fieldWidth: CARDINAL] RETURNS [newField, newnField: BitDWord] = TRUSTED {
s: SwitchTypes.Strength ← IF access THEN drive ELSE none;
IF access THEN FOR i:CARDINAL IN [0..fieldWidth) DO
field ← IBID[(NOT EBFD[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
nfield ← IBID[(NOT EBFD[field, fieldWidth, i]) AND nBusD[i].val=H, nfield, fieldWidth, i];
field ← IBID[(NOT EBFD[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
ENDLOOP;
SCDTS[field, fieldWidth, 0, fieldWidth, nBusD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
SCDTS[nfield, fieldWidth, 0, fieldWidth, busD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
newField ← field;
newnField ← nfield;
};
RWM: PROC [access: BOOL, busD, nBusD: SwitchMWord, field, nfield: BitMWord, fieldWidth: CARDINAL] = TRUSTED {
s: SwitchTypes.Strength ← IF access THEN drive ELSE none;
IF access THEN FOR i:CARDINAL IN [0..fieldWidth) DO
IBIM[(NOT EBFM[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
IBIM[(NOT EBFM[field, fieldWidth, i]) AND nBusD[i].val=H, nfield, fieldWidth, i];
IBIM[(NOT EBFM[nfield, fieldWidth, i]) AND busD[i].val=H, field, fieldWidth, i];
ENDLOOP;
SCMTS[field, fieldWidth, 0, fieldWidth, nBusD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
SCMTS[nfield, fieldWidth, 0, fieldWidth, busD, fieldWidth, 0, fieldWidth, [[none, X], [s, L]]];
};
Assert[NOT MoreThanOneOf[PAdrLow, nPAdrLow]];
Assert[NOT MoreThanOneOf[MAdrLow, nMAdrLow]];
Assert[MAdrLow OR nMAdrLow];
Assert[NOT MoreThanOneOf[VictimFeedback, ShiftVictim]];
Assert[NOT MoreThanOneOf[VictimFeedback, nVictimFeedback]];
Assert[NOT MoreThanOneOf[ShiftVictim, nShiftVictim]];
Assert[NOT MoreThanOneOf[ShiftVictim, PhBb]];
FOR i:[0..2) IN [0..2) DO
oldMemBits[i] ← data[i][TRUE];
ENDLOOP;
vpMatch ← DAND[nVirtualPage, virtualPage]=BitDWordZero AND DAND[nvirtualPage, VirtualPage]=BitDWordZero;
vblMatch ← WAND[nVirtualBlock, block]=0 AND WAND[nblock, VirtualBlock]=0;
rpMatch ← DAND[nRealPage, realPage]=BitDWordZero AND DAND[nrealPage, RealPage]=BitDWordZero;
rblMatch ← WAND[nRealBlock, block]=0 AND WAND[nblock, RealBlock]=0;
selVMap ← NOT broken AND vpValid AND vpMatch;
vSelCell ← selVMap AND vblMatch;
selRMap ← NOT broken AND rpValid AND rpMatch;
rSelCell ← selRMap AND rblMatch;
IF selVMap AND PhBb THEN {
nMapValid ← FALSE;
IF nrpDirty THEN nMatchPageClean ← FALSE;
};
IF rSelCell AND PhBb THEN nRealMatch ← FALSE;
decodeSelect ← SelCell AND CellAdr=thisCellAdr AND CellAdr=WNOT[nCellAdr, 8];
victimAdrSelect ← SelVictimAdr AND victim;
victimDataSelect ← SelVictimData AND victim;
realMatchSelect ← SelRealData AND rSelCell;
IF NOT PhAb THEN dataSelect ← FALSE;
IF decodeSelect OR realMatchSelect OR victimDataSelect OR ForceDataSelect THEN dataSelect ← TRUE;
IF NOT PhAb THEN victimFlagSelect ← FALSE;
IF decodeSelect OR ForceDataSelect THEN victimFlagSelect ← TRUE;
IF NOT PhAb THEN addressSelect ← FALSE;
IF decodeSelect OR victimAdrSelect THEN addressSelect ← TRUE;
IF PhBb AND vSelCell THEN {
nVirtualMatch ← FALSE;
IF PStore AND rpDirty AND (nshared OR FinishSharedStore) THEN {master ← TRUE; nmaster ← FALSE};
IF shared THEN nMatchCellShared ← FALSE;
IF tip THEN nMatchTIP ← FALSE;
};
TRUSTED {
busD: SwitchMWord ← DESCRIPTOR[PBits];
nBusD: SwitchMWord ← DESCRIPTOR[nPBits];
access: BOOL ← PhBb AND vSelCell AND (NOT (PStore AND (nrpDirty OR (shared AND NOT FinishSharedStore))));
IF NOT PAdrLow THEN { -- mumbo jumbo to ensure that at least one of these if clauses executes so that the instructions get updated
dataFD: BitMWord ← DESCRIPTOR[data[0][FALSE]];
dataTD: BitMWord ← DESCRIPTOR[data[0][TRUE]];
RWM[access AND nPAdrLow, busD, nBusD, dataTD, dataFD, 66];
};
IF PAdrLow THEN {
dataFD: BitMWord ← DESCRIPTOR[data[1][FALSE]];
dataTD: BitMWord ← DESCRIPTOR[data[1][TRUE]];
RWM[access, busD, nBusD, dataTD, dataFD, 66];
};
};
TRUSTED {
busD: SwitchMWord ← DESCRIPTOR[MBits];
nBusD: SwitchMWord ← DESCRIPTOR[nMBits];
access: BOOL ← dataSelect;
IF nMAdrLow THEN {
dataFD: BitMWord ← DESCRIPTOR[data[0][FALSE]];
dataTD: BitMWord ← DESCRIPTOR[data[0][TRUE]];
RWM[access, busD, nBusD, dataTD, dataFD, 66];
};
IF MAdrLow THEN {
dataFD: BitMWord ← DESCRIPTOR[data[1][FALSE]];
dataTD: BitMWord ← DESCRIPTOR[data[1][TRUE]];
RWM[access, busD, nBusD, dataTD, dataFD, 66];
};
[RPValid, nRPValid, rpValid, nrpValid] ← RWB[access, RPValid, nRPValid, rpValid, nrpValid];
[Master, nMaster, master, nmaster] ← RWB[access, Master, nMaster, master, nmaster];
[Shared, nShared, shared, nshared] ← RWB[access, Shared, nShared, shared, nshared];
[TIP, nTIP, tip, ntip] ← RWB[access, TIP, nTIP, tip, ntip];
[Broken, nBroken, broken, nbroken] ← RWB[access, Broken, nBroken, broken, nbroken];
};
{
access: BOOL ← victimFlagSelect;
[Victim, nVictim, victim, nvictim] ← RWB[access AND NOT (thisCellAdr=0 AND Resetb), Victim, nVictim, victim, nvictim];
};
{
access: BOOL ← dataSelect OR (SelPageFlag AND selRMap);
[VPValid, nVPValid, vpValid, nvpValid] ← RWB[access, VPValid, nVPValid, vpValid, nvpValid];
[RPDirty, nRPDirty, rpDirty, nrpDirty] ← RWB[access, RPDirty, nRPDirty, rpDirty, nrpDirty];
};
TRUSTED {
busD: SwitchMWord ← DESCRIPTOR[CAMPageAccess];
nBusD: SwitchMWord ← DESCRIPTOR[nCAMPageAccess];
[virtualPage, nvirtualPage] ← RWD[(addressSelect AND VirtualAccess) OR (rSelCell AND SelRealAdr), busD, nBusD, virtualPage, nvirtualPage, 24];
};
TRUSTED {
busD: SwitchMWord ← DESCRIPTOR[CAMPageAccess];
nBusD: SwitchMWord ← DESCRIPTOR[nCAMPageAccess];
[realPage, nrealPage] ← RWD[(addressSelect AND nVirtualAccess) OR (selVMap AND SelMapAdr), busD, nBusD, realPage, nrealPage, 24];
};
TRUSTED {
busD: SwitchMWord ← DESCRIPTOR[CAMBlockAccess];
nBusD: SwitchMWord ← DESCRIPTOR[nCAMBlockAccess];
[block, nblock] ← RWW[addressSelect, busD, nBusD, block, nblock, 6];
};
IF ShiftVictim THEN nvictim ← NOT VictimIn;
IF VictimFeedback THEN nvictim ← NOT victim;
IF PhBb THEN victim ← NOT nvictim; -- this is where nPhBb is used
VictimOut ← IF broken THEN VictimIn ELSE victim;
IF victim AND nmaster AND PhBb THEN nVictimClean ← FALSE;
IF thisCellAdr=0 AND Resetb THEN {
victim ← TRUE;
nvictim ← FALSE;
};
hexVirtualPage ← ELFD[virtualPage, 24, 0, 24];
hexRealPage ← ELFD[realPage, 24, 0, 24];
hexBlock ← ELFW[block, 6, 0, 6];
TRUSTED {
assembleWord: BitDWord;
diff: BOOL ← FALSE;
FOR i:[0..2) IN [0..2) DO
IF oldMemBits[i]#data[i][TRUE] THEN {diff ← TRUE; EXIT};
ENDLOOP;
IF diff OR Resetb THEN FOR k:[0..2) IN [0..2) DO
FOR j:[0..2) IN [0..2) DO
desc: BitMWord ← DESCRIPTOR[data[j][TRUE]];
FOR i:[0..32) IN [0..32) DO
assembleWord ← IBID[EBFM[desc, 66, (2*i)+k], assembleWord, 32, i];
ENDLOOP;
words[2*k+j] ← ELFD[assembleWord, 32, 0, 32];
parity[2*k+j] ← EBFM[desc, 66, 64+k];
ENDLOOP;
ENDLOOP;
}
END;
END;
CacheEntryPorts: Ports ← NEW [PortsRep[69]];
RegisterCells[];
END.