DIRECTORY CMosB, CoreClasses, CoreCreate, CoreFlat, CoreIO, CoreProperties, Dragon, EU, EUArith, EUInner, EUUtils, PadFrame, Ports, PWCore, Rosemary, Sisyph; BICSimImpl: CEDAR PROGRAM IMPORTS CoreClasses, CoreCreate, CoreFlat, CoreIO, CoreProperties, EUArith, EUInner, EUUtils, PadFrame, Ports, PWCore, Rosemary EXPORTS EU = BEGIN OPEN EU, CoreCreate; BICName: ROPE = Rosemary.Register[roseClassName: "BIC", init: BICInit, evalSimple: BICSimple]; AssertionFailed: SIGNAL [message: ROPE] = CODE; MoreThanOne: PROC [a, b, c, d: BOOL _ FALSE] RETURNS [BOOL _ FALSE] ~ { BtoN: PROC [b: BOOL] RETURNS [NAT] ~ {RETURN[IF b THEN 1 ELSE 0]}; RETURN[BtoN[a]+BtoN[b]+BtoN[c]+BtoN[d]>1]; }; CreateBIC: PUBLIC PROC RETURNS [ct: CellType ] = { ct _ CoreClasses.CreateUnspecified[public, BICName]; [] _ Rosemary.BindCellType[cellType: cellType, roseClassName: EUName]; [] _ CoreFlat.CellTypeCutLabels[cellType, "BIC"]; Ports.InitPorts[ct, l, none, "Vdd", "Gnd", "Gnd2V", "CKRecAdj", "RecAdj"]; Ports.InitPorts[cellType, lc, none, "DPData", "KBus"]; Ports.InitPorts[cellType, c, none, "EUAluOp2AB", "EUCondSel2AB"]; Ports.InitPorts[cellType, b, drive, "EUCondition2B", "DShOut"]; }; BICState: TYPE = REF BICStateRec; BICStateRec: TYPE = RECORD[ Vdd, Gnd, Gnd2V, CKRecAdj, RecAdj, Name, nDInB, nDOutB, nRqOutB, nOrOutB, nBInB, nBOutB, DOutH, DInH, RqIn, OrInH, BOutH, BInH, nEClock, Clock, LocCKOut, ExtCKOut, ChipCKIn, ExtCKIn, ChipCKOut, DCS, DBusIn, DBusOut, nSStop, DOEn, Send: NAT _ LAST[NAT], -- ports indexes prevCK: Ports.Level _ L, -- to detect edges normal, freeze, shift, reset: Ports.Level _ L, -- control for slices nBMaster2V, nBSlave2V: Ports.LevelSequence _ NIL, -- from B to H nBMaster5V, nBSlave5V: Ports.LevelSequence _ NIL, -- from H to B nOrMaster5V, nOrSlave5V: Ports.LevelSequence _ NIL, -- from H to B nRqMaster5V, nRqSlave5V: Ports.Level _ X, -- from H to B last: NAT _ 0 ]; BICInit: Rosemary.InitProc = { state: BICState _ NEW[BICStateRec]; {OPEN state; [Vdd, Gnd, Gnd2V, CKRecAdj, RecAdj, Name] _ Ports.PortIndexes[cellType.public, "Vdd", "Gnd", "Gnd2V", "CKRecAdj", "RecAdj", "Name"]; [nEClock, Clock, LocCKOut, ExtCKOut, ChipCKIn, ExtCKIn, ChipCKOut] _ Ports.PortIndexes[cellType.public, "nEClock", "Clock", "LocCKOut", "ExtCKOut", "ChipCKIn", "ExtCKIn", "ChipCKOut"]; [nDInB, nDOutB, nRqOutB, nOrOutB, nBInB, nBOutB] _ Ports.PortIndexes[cellType.public, "nDInB", "nDOutB", "nRqOutB", "nOrOutB", "nBInB", "nBOutB"]; [DOutH, DInH, RqIn, OrInH, BOutH, BInH] _ Ports.PortIndexes[cellType.public, "DOutH", "DInH", "RqIn", "OrInH", "BOutH", "BInH"]; [DCS, DBusIn, DBusOut, nSStop, DOEn, Send] _ Ports.PortIndexes[cellType.public, "DCS", "DBusIn", "DBusOut", "nSStop", "DOEn", "Send"]; }; stateAny _ state; }; BICSimple: Rosemary.EvalProc = { state: BICState _ NARROW[stateAny]; {OPEN state; Assert: PROC [condition: BOOL, message: ROPE _ NIL] = {IF NOT condition THEN SIGNAL AssertionFailed[message]}; RisingEdge: PROC [prev: Ports.Level, present: NAT] RETURNS [BOOL] ~ { RETURN[prevCK=L AND p[ChipCKIn].l=H]; }; Assert[p[Gnd].l=L AND p[Gnd2V].l=L]; Assert[p[Vdd].l=H AND p[CKRecAdj].l=H AND p[RecAdj].l=H]; p[ChipCKOut].l _ p[ChipCKIn].l; p[ExtCKOut].l _ p[LocCKOut].l _ Ports.NotL[p[nEClock].l]; FOR i: NAT IN p[nDInB].ls.size DO p[DOutH].ls[i] _ Ports.NotL[p[nDInB].ls[i]]; p[nBOutB].ls[i] _ Ports.NotL[Ports.AndL[p[DInH].ls[i], p[DOEn].l]]; ENDLOOP; Assert[normal#X AND freeze#X AND shift#X AND reset#X]; Assert[NOT MoreThanOne[normal=H, freeze=H, shift=H, reset=H]; SELECT p[ChipCKIn].l FROM L => SELECT TRUE FROM -- sample normal=H => { Ports.CopyLS[from: p[nBInB].ls, to: nBMaster2V]; Ports.CopyLS[from: p[BInH].ls, to: nBMaster5V]; Ports.CopyLS[from: p[RqIn].ls, to: nRqMaster5V]; nOrMaster5V _ Ports.OrL[ -- 4-input OR Ports.OrL[p[OrInH].ls[0], p[OrInH].ls[1]], Ports.OrL[p[OrInH].ls[2], p[OrInH].ls[3]]]; }; freeze=H => {}; shift=H => {}; reset=H => {}; ENDCASE => ERROR; ; H => SELECT TRUE FROM -- drive normal=H => {}; freeze=H => {}; shift=H => {}; reset=H => {}; ENDCASE => ERROR; ; ENDCASE => Statement; }}; END. BICSimImpl.mesa Copyright س 1987 by Xerox Corporation. All rights reserved. Louis Monier April 27, 1987 6:59:16 pm PDT Last Edited by: Louis Monier April 28, 1987 1:49:37 am PDT -- Check that everything is well hooked up -- Straight through -- Control of slices -- Slices ‌ت·– "cedar" styleکcodeڑœ™Kڑœ<™