BICSimImpl.mesa
Copyright Ó 1987 by Xerox Corporation. All rights reserved.
Louis Monier April 27, 1987 6:59:16 pm PDT
Last Edited by: Louis Monier April 28, 1987 1:49:37 am PDT
DIRECTORY CMosB, CoreClasses, CoreCreate, CoreFlat, CoreIO, CoreProperties, Dragon, EU, EUArith, EUInner, EUUtils, PadFrame, Ports, PWCore, Rosemary, Sisyph;
BICSimImpl:
CEDAR
PROGRAM
IMPORTS CoreClasses, CoreCreate, CoreFlat, CoreIO, CoreProperties, EUArith, EUInner, EUUtils, PadFrame, Ports, PWCore, Rosemary
EXPORTS EU =
BEGIN OPEN EU, CoreCreate;
BICName: ROPE = Rosemary.Register[roseClassName: "BIC", init: BICInit, evalSimple: BICSimple];
AssertionFailed: SIGNAL [message: ROPE] = CODE;
MoreThanOne:
PROC [a, b, c, d:
BOOL ←
FALSE]
RETURNS [
BOOL ←
FALSE] ~ {
BtoN:
PROC [b:
BOOL]
RETURNS [
NAT] ~ {
RETURN[
IF b
THEN 1
ELSE 0]};
RETURN[BtoN[a]+BtoN[b]+BtoN[c]+BtoN[d]>1];
};
CreateBIC:
PUBLIC
PROC
RETURNS [ct: CellType ] = {
ct ← CoreClasses.CreateUnspecified[public, BICName];
[] ← Rosemary.BindCellType[cellType: cellType, roseClassName: EUName];
[] ← CoreFlat.CellTypeCutLabels[cellType, "BIC"];
Ports.InitPorts[ct, l, none, "Vdd", "Gnd", "Gnd2V", "CKRecAdj", "RecAdj"];
Ports.InitPorts[cellType, lc, none, "DPData", "KBus"];
Ports.InitPorts[cellType, c, none, "EUAluOp2AB", "EUCondSel2AB"];
Ports.InitPorts[cellType, b, drive, "EUCondition2B", "DShOut"];
};
BICState: TYPE = REF BICStateRec;
BICStateRec:
TYPE =
RECORD[
Vdd, Gnd, Gnd2V, CKRecAdj, RecAdj, Name, nDInB, nDOutB, nRqOutB, nOrOutB, nBInB, nBOutB, DOutH, DInH, RqIn, OrInH, BOutH, BInH, nEClock, Clock, LocCKOut, ExtCKOut, ChipCKIn, ExtCKIn, ChipCKOut, DCS, DBusIn, DBusOut, nSStop, DOEn, Send: NAT ← LAST[NAT], -- ports indexes
prevCK: Ports.Level ← L, -- to detect edges
normal, freeze, shift, reset: Ports.Level ← L, -- control for slices
nBMaster2V, nBSlave2V: Ports.LevelSequence ← NIL, -- from B to H
nBMaster5V, nBSlave5V: Ports.LevelSequence ← NIL, -- from H to B
nOrMaster5V, nOrSlave5V: Ports.LevelSequence ← NIL, -- from H to B
nRqMaster5V, nRqSlave5V: Ports.Level ← X, -- from H to B
last: NAT ← 0
BICInit: Rosemary.InitProc = {
state: BICState ← NEW[BICStateRec];
{
OPEN state;
[
Vdd, Gnd, Gnd2V, CKRecAdj, RecAdj, Name] ←
Ports.PortIndexes[cellType.public, "Vdd", "Gnd", "Gnd2V", "CKRecAdj", "RecAdj", "Name"];
[
nEClock, Clock,
LocCKOut,
ExtCKOut,
ChipCKIn,
ExtCKIn,
ChipCKOut] ←
Ports.PortIndexes[cellType.public, "nEClock", "Clock", "LocCKOut", "ExtCKOut", "ChipCKIn", "ExtCKIn", "ChipCKOut"];
[
nDInB,
nDOutB, nRqOutB, nOrOutB, nBInB, nBOutB] ←
Ports.PortIndexes[cellType.public, "nDInB", "nDOutB", "nRqOutB", "nOrOutB", "nBInB", "nBOutB"];
[
DOutH,
DInH, RqIn, OrInH, BOutH, BInH] ←
Ports.PortIndexes[cellType.public, "DOutH", "DInH", "RqIn", "OrInH", "BOutH", "BInH"];
[DCS, DBusIn, DBusOut, nSStop, DOEn, Send] ←
Ports.PortIndexes[cellType.public, "DCS", "DBusIn", "DBusOut", "nSStop", "DOEn", "Send"];
};
stateAny ← state;
};
BICSimple: Rosemary.EvalProc = {
state: BICState ← NARROW[stateAny];
{OPEN state;
Assert:
PROC [condition:
BOOL, message:
ROPE ←
NIL] =
{IF NOT condition THEN SIGNAL AssertionFailed[message]};
RisingEdge:
PROC [prev: Ports.Level, present:
NAT]
RETURNS [
BOOL] ~ {
RETURN[prevCK=L AND p[ChipCKIn].l=H];
};
-- Check that everything is well hooked up
Assert[p[Gnd].l=L AND p[Gnd2V].l=L];
Assert[p[Vdd].l=H AND p[CKRecAdj].l=H AND p[RecAdj].l=H];
-- Straight through
p[ChipCKOut].l ← p[ChipCKIn].l;
p[ExtCKOut].l ← p[LocCKOut].l ← Ports.NotL[p[nEClock].l];
FOR i: NAT
IN p[nDInB].ls.size
DO
p[DOutH].ls[i] ← Ports.NotL[p[nDInB].ls[i]];
p[nBOutB].ls[i] ← Ports.NotL[Ports.AndL[p[DInH].ls[i], p[DOEn].l]];
ENDLOOP;
-- Control of slices
Assert[normal#X AND freeze#X AND shift#X AND reset#X];
Assert[NOT MoreThanOne[normal=H, freeze=H, shift=H, reset=H];
-- Slices
SELECT p[ChipCKIn].l
FROM
L =>
SELECT
TRUE
FROM
-- sample
normal=H => {
Ports.CopyLS[from: p[nBInB].ls, to: nBMaster2V];
Ports.CopyLS[from: p[BInH].ls, to: nBMaster5V];
Ports.CopyLS[from: p[RqIn].ls, to: nRqMaster5V];
nOrMaster5V ← Ports.OrL[ -- 4-input OR
Ports.OrL[p[OrInH].ls[0], p[OrInH].ls[1]],
Ports.OrL[p[OrInH].ls[2], p[OrInH].ls[3]]];
};
freeze=H => {};
shift=H => {};
reset=H => {};
ENDCASE => ERROR;
;
H =>
SELECT
TRUE
FROM
-- drive
normal=H => {};
freeze=H => {};
shift=H => {};
reset=H => {};
ENDCASE => ERROR;
;
ENDCASE => Statement;
}};
END.