<> <> <> <> <<>> DIRECTORY Core, CoreFlat, IO, Rope, Rosemary, RosemaryUser, Ports, TerminalIO; BICSim: CEDAR PROGRAM IMPORTS CoreFlat, RosemaryUser, Ports = BEGIN <> ROPE: TYPE = Rope.ROPE; nbCycles: INT _ 0; nIn2V, nOut2V, In5V, Out5V, -- 21 bits nDIn2V, nDOut2V, DIn5V, DOut5V, -- 2 bits nRqIn2V, nRqOut2V, RqIn5V, RqOut5V, -- 2 bits nShrIn2V, nShrOut2V, ShrOut5V, -- 1 bit ShrIn5V, -- 4 bits CS, ChipID, -- 3 bits Grant, -- 4 bits DriverEnable, HybridSelect, DFreeze, nDExecute, DShift, DReset, Address, DataIn, DataOut, Vdd, Gnd, Gnd2V, Vth, ClockRef, CK, ClockIn, ClockOut: NAT _ LAST[NAT]; Initialize: PROC [p: Ports.Port, public: Core.Wire] = { InitializePublic[public]; }; InitializePublic: PROC [public: Core.Wire] = { [In2V, Out2V, In5V, Out5V] _ Ports.PortIndexes[public, "In2V", "Out2V", "In5V", "Out5V"]; [DIn2V, DOut2V, DIn5V, DOut5V] _ Ports.PortIndexes[public, "DIn2V", "DOut2V", "DIn5V", "DOut5V"]; [RqIn2V, RqOut2V, RqIn5V, RqOut5V] _ Ports.PortIndexes[public, "RqIn2V", "RqOut2V", "RqIn5V", "RqOut5V"]; [ShrIn2V, ShrOut2V, ShrOut5V, ShrIn5V] _ Ports.PortIndexes[public, "ShrIn2V", "ShrOut2V", "ShrOut5V", "ShrIn5V"]; [CS, ChipID, Grant] _ Ports.PortIndexes[public, "CS", "ChipID", "Grant"]; [DriverEnable, HybridSelect, DFreeze, DExecute, DShift, DReset, Address, DataIn, DataOut] _ Ports.PortIndexes[public, "DriverEnable", "HybridSelect", "DFreeze", "DExecute", "DShift", "DReset", "Address", "DataIn", "DataOut"]; }; ExerciseRose: PUBLIC PROC [ct: Core.CellType, cutSets: LIST OF ROPE _ NIL] RETURNS [tester: RosemaryUser.Tester] = { InitializePublic[ct.public]; tester _ RosemaryUser.TestProcedureViewer[ cellType: ct, testButtons: LIST["BICTest"], name: "BICTest", displayWires: RosemaryUser.DisplayPortLeafWires[ct], cutSet: CoreFlat.CreateCutSet[labels: cutSets], steady: FALSE]; }; DoCK: PROC [p: Ports.Port, Eval: PROC] = { nbCycles _ nbCycles+1; p[ClockRef].b _ FALSE; Eval[]; p[ClockRef].b _ TRUE; Eval[]; }; Ignore: PROC [p: Ports.Port, port: NAT] ~ {p[port].d _ none}; Force: PROC [p: Ports.Port, port: NAT, val: LONG CARDINAL] ~ {p[port].d _ force; p[port].lc _ val}; Expect: PROC [p: Ports.Port, port: NAT, val: LONG CARDINAL] ~ {p[port].d _ expect; p[port].lc _ val}; Reset: PROC [p: Ports.Port, Eval: PROC, nbCycles: NAT] ~ { p[DReset].b _ TRUE; THROUGH [0..nbCycles) DO DoCK[p, Eval ! Ports.CheckError => RESUME]; ENDLOOP; }; <<>> <<>> <<-- Test procs>> <<>> <<-- The minimum expected from a chip>> BICTest: RosemaryUser.TestProc = { Reset[p, Eval, 10]; -- reset for 10 cycles }; IF TRUE THEN RosemaryUser.RegisterTestProc["BICTest", BICTest]; END.