[Indigo]<Dragon>BIC>BICDoc.tioga!1

DRAGON DOCUMENT TITLE

DRAGON PROJECT — FOR INTERNAL XEROX USE ONLY

Bus Interface Chip

Subtitle, if any

Richard Bruce, Louis Monier

Dragon-86-xx Written February 1987 Revised Month, Year

Abstract: The Bus Interface Chip (BIC) is a component of the June87 machine. It connects the other chips on their hybrid (cache, memory controller, IOBridge, display controller) to the fast 2V bus.

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FileName: /Indigo/Dragon/BIC/BICDoc.tioga, .interpress

XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304

Dragon Project - For Internal Xerox Use Only

Contents

1. Introduction

2. Pinout

3. Block Diagram

4. Signals definition

5. Timing

6. Application schematics

Appendix A. Appendix A Title

Appendix B. Appendix B Title

ChangeLog

1. Overview

The two main functions of the Interface Chip are: to connect the logic and memory operations to the DynaBus on the printed circuit board (PCB) and to connect the DynaBus (PCB) to the DynaBus on the backplane (BP). Signals are registered when entering and just before leaving hybrids at the PCB interface, and these registers are scanable by the DBus. Signals are not registered at the hybrid PB interface. In addition the DBus control logic, and the clock amplification stages for a hybrid are located on the chip.

Three different kinds of recievers and drivers have been designed. First to interface all nonDBus communication, there are 22 drivers and receivers whose contents are registered and DBus scannable. The drivers are activated by GrantRelease with the exception of one which is attached to a 4 input OR gate. To connect the BP to the bridge hybrid, there are 22 drivers and receivers which have no registers. Finally there are 4 drivers and receivers which are registered but not scanned to handle the DBus communication. These receivers send the DBus address and control lines to all of the chips on the hybrid and the drivers send the DBus output onto the DynaBus.

The chip uses edge triggered flip-flops for registers. A capacitance ratio of 4 has been used for successive stages. All IO paths interface with the 2V bus with the same receivers and drivers.

2. Parts

2.1 Guide to viewing

The design has several layers of heirarchy. The various icons and corresponding schematics are displayed together as cells. The cells are arranged in groups: the overview, the nonDBus IO, the DBus parts, and the clock.

2.2 InterfaceChip

The interface chip icon is derived from the interface chip schematic and contains all of the IO pins of the chip. The icon is displayed with the IO functions on one end, the DBus control in the middle and the clock amplifiers on the bottom. On one side are 2V signals (with the exception of clock and hybrid definition lines), and on the other side are 5V signals.

2.3 Wired Drivers and Receivers (Scanned and Registered), DBus Control and ID (IOL&ID)

The top level schematic for the 22 registered/scanned drivers and receivers is shown here. Note that DBus out is controled by chipselect and that the DynaBus driver whose input is the 4InputOR gate (0/22) is not controlled by grant release. There is a test line (TestOut) which is the exclusive OR conbination of all the receiver outputs with the values of the driver inputs. The Grant Release is the output of a 4 input OR gate. A 4 wire bus (4InOR) is provided for error, shared and owner.

2.4 Wired Drivers and Receivers Scanned and Registered (IORec&Driver)

The registered and scanned receiver and driver appear in pairs to uniformily spread the current requirements. This schematics shows how these functions are wired to themselves, the DBus, the DynaBus and the hybrid.

2.5 Bus Receiver

The bus receiver attaches to the bus through the source on an nMOS transistor whose gate voltage (Vset) is externally set to a value around 2V while the drain is connected to the input of an inverter and the drain of a pMOS pull-up. When the bus voltage drops below Vset-Vth, the nMOS transistor is conducting and the pull-up current is sunk through the active bus driver. When no driver is pulling the bus down the nMOS transistor is off and the pull-up drain goes high.

The bus signal is latched after 4 stages of propagation and is sent off on the hybrid after two. The receiver is designed to drive a hybrid load of 10pF.

The data is inverted in these IO devices. The DynaBus contains nData and the hybrid contains Data.

2.6 Bus Driver

The bus driver drives the bus through the drain of an nMOS transistor. This transistor is driven directly by the flip-flop register so there are two stages of propogation delay. The driver input is activated by GrantRelease so that only chips granted access to the bus will be able to transmit. There are 3 stages of delay from the input to the register flip-flop.

The data is inverted in these IO devices. The DynaBus contains nData and the hybrid contains Data.

2.7 Device ID

The device ID registers a predefined level after two stages of delay. This level is also registered during reset.

2.8 Backplane Driver (DriverNL)

This driver is a single open-drain nMOS transistor which drives the packplane from the bridge hybrid. It is the same driver as is used to drive the DynaBuse on the PCB.

The data is inverted in these IO devices. The DynaBus contains nData and the hybrid contains Data.

2.9 Backplane Receiver (RecNL)

This receiver is used to sense the backplane from the bridge hybrid. The receiver is the same as that used to sense the DynaBus on the PCB. The output of the receiver is expected to drive 10pF. There are 3 stages of propagation through the unit.

The data is inverted in these IO devices. The DynaBus contains nData and the hybrid contains Data.

2.10 DBus Control Logic (DBusCtl)

This logic is used to generate the DBus control signals. There are two stages of pipline in the logic which means naturaly that control signals are changed two cylcles after input signals change. Several assumptions are made on these signals. First Reset has highest priority and automatically turns off Freeze. Naturally shift also turns off Freeze as does Execute since these commands work in Freeze mode. Shift and Normal are high for one cycle respecively after nShift and nExecute transition low. This logic assumes that Freeze is activated whenever Execute or Shift are used

2.11 Chip Select Generation Logic (ChipSelGenUnit)

The chip select signal is generated in this unit from DBus address signals and a hybrid select signal. Each interface chip on a hybrid has a unique hardwired ID number and each hybrid has a unique bus line from the arbiter. The DBus adresses are registered after one stage of propagation; however, there are at least 6 stages of propagation to drive a signal off chip. The unit is designed to drive 10pF of capacitance.

2.12 DBus Driver

The DBus driver is designed to transmit DBus output onto the DynaBus. The signals are registered but not DBus scanned. There are three stages of progagation for a signal from the hybrid to be registered. There are two stages of progagation for the signal to reach the DynaBus.

The data is inverted in these IO devices. The DynaBus contains nData and the hybrid contains Data.

2.13 DBus Receiver (DBusRec)

The DBus receiver inputs DynaBus DBus signals to the hybrid. There are 3 stages of delay to the register and three stages to the hybrid. The chip is designed to drive 25pF on the hybrid since some of the signals will go to each chip.

The data is inverted in these IO devices. The DynaBus contains nData and the hybrid contains Data.

2. Pinout

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2.1 SubSection Title

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2.2 SubSection Title

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3. Block Diagram

3.1 SubSection Title

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3.2 SubSection Title

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4. Signals definition

4.1 Power supplies

The BIC uses two sets of power supplies: Vdd (+5V) and Gnd (0V) for the logic and the hybrid pad drivers, and Gnd2V (0V) for the Dynabus drivers. The two Gnd are not connected on the chip to prevent spikes generated when driving the Dynabus to affect the logic.

The threshold in the Dynabus receivers is controlled by an external analog voltage Vth.

4.2 Clocks

The BIC receives a reference clock (ClockRef) which is amplified once and delivers a high-power clock (ClockOut) to all the other chips on the hybrid, including itself. This signal is routed externally back as ClockIn and amplified in two stages in every chip to become the standard clock CK.

4.3 Debug bus

Standard interface to the DBus. DExecute means single step. 5-bit shift register for address. CS and ChipID. DriverEnable???

4.4 Communication with the hybrid

There are 26 pairs of 5V driver/receivers. Load is 20pF, except for DBus signals.

In5V[0..21), Out5V[0..21),

DIn5V[0..2), DOut5V[0..2),

RqIn5V[0..2), RqOut5[0..2),

ShrIn5V[0..4), ShrOut5V

4.5 Communication with the arbiter

Grant[0..4).

4.6 Communication with the Dynabus

There are 26 pairs of 2V driver/receivers.

nIn2V[0..21), nOut2V[0..21),

nDIn2V[0..2), nDOut2V[0..2),

nRqIn2V[0..2), nRqOut2V[0..2),

nShrIn2V, nShrOut2V,

Appendix A. Appendix A Title

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Appendix B. Appendix B Title

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ChangeLog

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