BIC.log
Last Edited by: Louis Monier May 1, 1987 2:19:38 pm PDT
4/22:
Added two spare pads and a lot of power pads.
Complete routing with NewCabbage.
Passed MintCheck and Static.
Passed Lichen on all cells:
pb with DBusSlice and normalSlice
pb as expected with chargePump (series transistors)
4/23:
Added two spare pads
Generation failed in PWPins with a pin of size 0 => Rewrote the obstacle avoidance part of NewCabbage with Brian => finally generate the complete layout BICLayout.dale
Plot BIC.dale and BICLayout.dale
Fixed LogicRosemaryImpl to be able to simulate at transistor level
Passed MintCheck on BIC.icon: no problem. 5980 fat transistors, 2964 nodes.
4/24:
Routing bugs and missing pins in pads => new generation.
Fixed a few cells (Genista) and modified (Bill G. request)
Simulation failed very mysteriously (Rosemary bug, or stale VM?)
4/25:
Raw extract and Static => OK.
Simulation: infinite loop in a SC ff ???
4/26:
Fixed pads for RawExtract (overglass pins). Modified a few cells (Bill. G.)
Made a cm file to Lichen all library cells; all cells for slices are OK.
4/27:
Router could not route DBusOut: exchanged it with spareLeft, and it works.
Created resistances for mimicking pull-ups on bus.
Rosemary sim at transistor level could not handle the edge-triggered oracle and circuit: the fix is to have two clocks, the oracle clock been 1/2 phase early from the circuit clock.
DRC of cells now OK.
Simulation found the following bugs:
the four wires of dpControl in DBusControl were inverted => now uses nQ instead of Q
in normalSlice, last driver on hybrid side (n=640) was missing => added the inv640
path from OrInH to nOrOutB was computing a NOR instead of an OR => added a Nand
Started writing BICSimImpl.mesa, a behavioral proc for BIC.
Completed the oracle file. Executed 300 cycles, then crashed while shifting.
Started a new layout.
4/28:
Found out from Mike Ov. and Bill G. that we might not get the 300 PGA. Will try to squeeze the chip to fit in a 14mm cavity.
Designed the last cells for the test chip.
4/29:
Lost my disk. Fixed the few bugs found by Richard. Decided not to touch the pad frame.
4/30:
Fixed more glitches. New layout generation completed successfuly. The truth could be
BIC.core!5 666444 30-Apr-87 20:33:29 PDT
BICLayout.dale!4 371088 30-Apr-87 20:35:48 PDT
5/1:
Mark found geometry on 1/4 and 1/8 micron. Culprit was the power rail whose size must be an odd number.
Redid layout.
Problem again: the piece of code in NewCabbage that "avoids obstacles" can dump wires on a 1/8 micron grid. Mark hacked the CIF gen to accept that.
Still to do:
Complete DRC (Mark)
Plot BICLayout.dale, rotated with a frame
Notes:
Chip definition: need at least a month when design is frozen; less => no time to do checks
Logic def
Simulation:
being exhaustive is almost free => test coverage
use non-symetric patterns
include transistor-level with no dynamic nodes
Layout:
Minimize at all cost the number of leave cells
For every block, have systematical layout rules => no overlap, no DRC bugs when assembling
Raw extraction, Static, Mintcheck, simulation
DRC:
on leaf cells as you go
Errors are simple: missing inverters, permute xor and xnor, a and aBar, ...
The best is the enemy of the good.