<> <> <> <<>> Library Gates, Latches, Transistors; CellType "RequestDrive" PORTS [Request, Grant, PhA, nPhA, PhB -- in -- =BIT, Keep, NoRequest, RqOut=BIT, nlRq -- out -- =BIT, Vdd, Gnd=BIT, BiasMinus, BiasPlus -- in -- =BIAS] Expand nRequest, lRequest, t1, t2, t3, t4: BIT; i1: Inverter[in: Request, out: nRequest]; l1: NonInvertingLatch[Clock: PhA, D: nRequest, Q: nlRq]; i2: Inverter[in: nlRq, out: lRequest]; k1: nE[gate: lRequest, ch1: t1, ch2: Keep]; k2: nE[gate: Grant, ch1: t2, ch2: t1]; k3: nE[gate: PhB, ch1: Gnd, ch2: t2]; n1: nE[gate: lRequest, ch1: t3, ch2: NoRequest]; n2: nE[gate: PhB, ch1: Gnd, ch2: t3]; s1: nE[gate: lRequest, ch1: t4, ch2: RqOut]; s2: nE[gate: PhB, ch1: Gnd, ch2: t4]; p1: StaticPrecharge[clock: nPhA, out: RqOut] EndCellType <<>>