<> <> <> <> <<>> IMPORTS Gates, IO, Transistors; Library Gates, Latches, Transistors; CellType "PriorityEncoder" PORTS [peIn0, peIn1, peIn2, peIn3, peIn4, peIn5, peIn6, peIn7, peIn8, peIn9, peIn10, peIn11, peIn12, peIn13, peIn14 -- in -- =BIT, peOut0, peOut1, peOut2, peOut3, peOut4, peOut5, peOut6, peOut7, peOut8, peOut9, peOut10, peOut11, peOut12, peOut13, peOut14, peOut15=BIT, nPhA, Vdd, Gnd=BIT, BiasPlus -- in -- =BIAS] Expand CEDAR FOR i: NAT IN [0..15) DO FOR j: NAT IN [0..i] DO [] _ to.class.CellInstance[erInstance: to.instance, instanceName: IO.PutFR["T%g-%g", IO.card[i], IO.card[j]], typeName: Transistors.nE.name, interfaceNodes: IO.PutFR["gate: peIn%g, ch1: Gnd, ch2: peOut%g", IO.card[j], IO.card[i+1]]]; ENDLOOP; [] _ to.class.CellInstance[erInstance: to.instance, instanceName: IO.PutFR["P%g", IO.card[i]], typeName: "StaticPrecharge", interfaceNodes: IO.PutFR["clock: nPhA, out: peOut%g", IO.card[i]]]; ENDLOOP; [] _ to.class.CellInstance[erInstance: to.instance, instanceName: "P15", typeName: "StaticPrecharge", interfaceNodes: "clock: nPhA, out: peOut15"]; EndCellType