<> <> <> <<>> Library Gates, Latches, Transistors; CellType "PreGrantDrive" PORTS [nlRequest, PhA, nPhA, PhB -- in -- =BIT, nPreGrant, NoGrant -- out -- =BIT, ShifterOut=BIT, Vdd, Gnd=BIT, BiasMinus, BiasPlus -- in -- =BIAS] Expand t1, t2, t3, PreGrant: BIT; n1: nE[gate: nlRequest, ch1: t1, ch2: ShifterOut]; n2: nE[gate: PhB, ch1: Gnd, ch2: t1]; i1: Inverter[in: ShifterOut, out: t2]; l1: DualRailLatch[Clock: PhB, D: t2, Q: nPreGrant, nQ: PreGrant]; n3: nE[gate: PhA, ch1: t3, ch2: NoGrant]; n4: nE[gate: PreGrant, ch1: Gnd, ch2: t3] EndCellType