<> <> <> <<>> Library Gates, Latches, Transistors; CellType "PEDrive" PORTS [ShifterOut -- in -- =BIT, encoderDrive -- out -- =BIT, Vdd, Gnd=BIT, BiasPlus -- in -- =BIAS] Expand i1: Inverter[in: ShifterOut, out: encoderDrive] EndCellType