MCmdDrive.Rose
Copyright (C) 1984 by Xerox Corp. All rights reserved.
Last Edited by: Gasbarro, August 17, 1984 10:59:43 am PDT
Last Edited by: Spreitzer, July 31, 1984 2:59:02 pm PDT
Library Gates, Latches, Transistors;
CellType "MCmdDrive"
PORTS [PhA, PhB, nPhB -- in -- =BIT, NoGrant=BIT, MCmd0, MCmd1, MCmd2, MCmd3=BIT, Vdd, Gnd=BIT, BiasMinus, BiasPlus -- in -- =BIAS]
Expand
t2, t3, t6, t7: BIT ← "H";
t1, t4, t5, t8, t9: BIT;
s1: StaticPrecharge[clock: nPhB, out: NoGrant];
i1: Inverter[in: NoGrant, out: t9];
l1: InvertingLatch[Clock: PhA, D: t9, nQ: t1];
g1: NAND[in1: t1, in2: PhB, out: t2];
g2: NAND[in1: t2, in2: t3, out: t4];
g3: OAI[ino1: PhA, ino2: t5, ina1: t4, out: t3];
g4: NAND[in1: t2, in2: t6, out: t5];
g5: NAND[in1: t5, in2: t7, out: t6];
i2: Inverter[in: PhA, out: t7];
i3: Inverter[in: t4, out: t8];
m0: pE[gate: t8, ch1: Vdd, ch2: MCmd0];
m1: pE[gate: t8, ch1: Vdd, ch2: MCmd1];
m2: pE[gate: t8, ch1: Vdd, ch2: MCmd2];
m3: pE[gate: t8, ch1: Vdd, ch2: MCmd3]
EndCellType