
<<LatchesWithPreset.Rose>>
<<Copyright (C) 1984 by Xerox Corp.  All rights reserved.>>
<<Last Edited by: Gasbarro, August 17, 1984 11:22:31 am PDT>>

Library Transistors;

CellType "InvertingLatchWithPreset"
PORTS [Clock, nPreset, D -- in -- =BIT, nQ -- out -- =BIT, Vdd, Gnd -- in -- =BIT, BiasMinus -- in -- =BIAS]
Expand
inl: BIT _ "H";
t1: BIT;
latch: nE[gate: Clock, ch1: D, ch2: inl];

pu1: pE[gate: inl, ch1: Vdd, ch2: nQ];
pd1: nE[gate: inl, ch1: Gnd, ch2: nQ];

pu2: wpu[gate: nQ, ch1: Vdd, ch2: inl];
pd2: nE[gate: nQ, ch1: t1, ch2: inl];
bias: wpd[gate: BiasMinus, ch1: Gnd, ch2: t1];
pu3: pE[gate: nPreset, ch1: Vdd, ch2: inl]
EndCellType;

CellType "NonInvertingLatchWithPreset"
PORTS [Clock, nPreset, D -- in -- =BIT, Q -- out -- =BIT, Vdd, Gnd -- in -- =BIT, BiasMinus -- in -- =BIAS]
Expand
inl: BIT _ "H";
t1: BIT _ "L";
t2: BIT;
latch: nE[gate: Clock, ch1: D, ch2: inl];

pu1: pE[gate: inl, ch1: Vdd, ch2: t1];
pd1: nE[gate: inl, ch1: Gnd, ch2: t1];

pu2: wpu[gate: t1, ch1: Vdd, ch2: inl];
pd2: nE[gate: t1, ch1: t2, ch2: inl];
bias: wpd[gate: BiasMinus, ch1: Gnd, ch2: t2];

pu3: pE[gate: t1, ch1: Vdd, ch2: Q];
pd3: nE[gate: t1, ch1: Gnd, ch2: Q];

pu4: pE[gate: nPreset, ch1: Vdd, ch2: inl]
EndCellType;

CellType "WeakNonInvertingLatchWithPreset"
PORTS [Clock, nPreset, D -- in -- =BIT, Q -- out -- =BIT, Vdd, Gnd -- in -- =BIT, BiasMinus -- in -- =BIAS]
Expand
t1: BIT _ "L";
t2: BIT;
latch: nE[gate: Clock, ch1: D, ch2: Q];

pu1: pE[gate: Q, ch1: Vdd, ch2: t1];
pd1: nE[gate: Q, ch1: Gnd, ch2: t1];

pu2: wpu[gate: t1, ch1: Vdd, ch2: Q];
pd2: nE[gate: t1, ch1: t2, ch2: Q];
bias: wpd[gate: BiasMinus, ch1: Gnd, ch2: t2];

pu3: pE[gate: nPreset, ch1: Vdd, ch2: Q]
EndCellType;

CellType "DualRailLatchWithPreset"
PORTS [Clock, nPreset, D -- in -- =BIT, Q, nQ -- out -- =BIT, Vdd, Gnd -- in -- =BIT, BiasMinus -- in -- =BIAS]
Expand
inl: BIT _ "H";
t1: BIT;
latch: nE[gate: Clock, ch1: D, ch2: inl];

pu1: pE[gate: inl, ch1: Vdd, ch2: nQ];
pd1: nE[gate: inl, ch1: Gnd, ch2: nQ];

pu2: wpu[gate: nQ, ch1: Vdd, ch2: inl];
pd2: nE[gate: nQ, ch1: t1, ch2: inl];
bias: wpd[gate: BiasMinus, ch1: Gnd, ch2: t1];

pu3: pE[gate: nQ, ch1: Vdd, ch2: Q];
pd3: nE[gate: nQ, ch1: Gnd, ch2: Q];

pu4: pE[gate: nPreset, ch1: Vdd, ch2: inl]
EndCellType;

CellType "WeakDualRailLatchWithPreset"
PORTS [Clock, nPreset, D -- in -- =BIT, Q, nQ -- out -- =BIT, Vdd, Gnd -- in -- =BIT, BiasMinus -- in -- =BIAS]
Expand
t1: BIT;
latch: nE[gate: Clock, ch1: D, ch2: Q];

pu1: pE[gate: Q, ch1: Vdd, ch2: nQ];
pd1: nE[gate: Q, ch1: Gnd, ch2: nQ];

pu2: wpu[gate: nQ, ch1: Vdd, ch2: Q];
pd2: nE[gate: nQ, ch1: t1, ch2: Q];
bias: wpd[gate: BiasMinus, ch1: Gnd, ch2: t1];

pu3: pE[gate: nPreset, ch1: Vdd, ch2: Q]
EndCellType