Latches.Rose
Copyright (C) 1984 by Xerox Corp. All rights reserved.
Last Edited by: Spreitzer, July 2, 1984 8:29:26 pm PDT
Last Edited by: Gasbarro, August 17, 1984 11:22:39 am PDT
Library Transistors;
CellType "InvertingLatch"
PORTS [Clock, D -- in -- =BIT, nQ -- out -- =BIT, Vdd, Gnd=BIT, BiasMinus -- in -- =BIAS]
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inl: BIT ← "H";
t1: BIT;
latch: nE[gate: Clock, ch1: D, ch2: inl];
pu1: pE[gate: inl, ch1: Vdd, ch2: nQ];
pd1: nE[gate: inl, ch1: Gnd, ch2: nQ];
pu2: wpu[gate: nQ, ch1: Vdd, ch2: inl];
pd2: nE[gate: nQ, ch1: t1, ch2: inl];
bias: wpd[gate: BiasMinus, ch1: Gnd, ch2: t1]
EndCellType;
CellType "NonInvertingLatch"
PORTS [Clock, D -- in -- =BIT, Q -- out -- =BIT, Vdd, Gnd -- in -- =BIT, BiasMinus -- in -- =BIAS]
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inl: BIT ← "H";
t1, t2: BIT;
latch: nE[gate: Clock, ch1: D, ch2: inl];
pu1: pE[gate: inl, ch1: Vdd, ch2: t2];
pd1: nE[gate: inl, ch1: Gnd, ch2: t2];
pu2: wpu[gate: t2, ch1: Vdd, ch2: inl];
pd2: nE[gate: t2, ch1: t1, ch2: inl];
bias: wpd[gate: BiasMinus, ch1: Gnd, ch2: t1];
pu3: pE[gate: t2, ch1: Vdd, ch2: Q];
pd3: nE[gate: t2, ch1: Gnd, ch2: Q]
EndCellType;
CellType "WeakNonInvertingLatch"
PORTS [Clock, D -- in -- =BIT, Q -- out -- =BIT, Vdd, Gnd -- in -- =BIT, BiasMinus -- in -- =BIAS]
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t1: BIT;
t2: BIT ← "H";
latch: nE[gate: Clock, ch1: D, ch2: Q];
pu1: pE[gate: Q, ch1: Vdd, ch2: t2];
pd1: nE[gate: Q, ch1: Gnd, ch2: t2];
pu2: wpu[gate: t2, ch1: Vdd, ch2: Q];
pd2: nE[gate: t2, ch1: t1, ch2: Q];
bias: wpd[gate: BiasMinus, ch1: Gnd, ch2: t1]
EndCellType;
CellType "DualRailLatch"
PORTS [Clock, D -- in -- =BIT, Q, nQ -- out -- =BIT, Vdd, Gnd -- in -- =BIT, BiasMinus -- in -- =BIAS]
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inl: BIT ← "H";
t1: BIT;
latch: nE[gate: Clock, ch1: D, ch2: inl];
pu1: pE[gate: inl, ch1: Vdd, ch2: nQ];
pd1: nE[gate: inl, ch1: Gnd, ch2: nQ];
pu2: wpu[gate: nQ, ch1: Vdd, ch2: inl];
pd2: nE[gate: nQ, ch1: t1, ch2: inl];
bias: wpd[gate: BiasMinus, ch1: Gnd, ch2: t1];
pu3: pE[gate: nQ, ch1: Vdd, ch2: Q];
pd3: nE[gate: nQ, ch1: Gnd, ch2: Q]
EndCellType;
CellType "WeakDualRailLatch"
PORTS [Clock, D -- in -- =BIT, Q, nQ -- out -- =BIT, Vdd, Gnd -- in -- =BIT, BiasMinus -- in -- =BIAS]
Expand
t1: BIT;
latch: nE[gate: Clock, ch1: D, ch2: Q];
pu1: pE[gate: Q, ch1: Vdd, ch2: nQ];
pd1: nE[gate: Q, ch1: Gnd, ch2: nQ];
pu2: wpu[gate: nQ, ch1: Vdd, ch2: Q];
pd2: nE[gate: nQ, ch1: t1, ch2: Q];
bias: wpd[gate: BiasMinus, ch1: Gnd, ch2: t1]
EndCellType