<> <> <> <<>> Library Gates, LatchesWithPreset, Transistors; CellType "GrantDriveRest" PORTS [nReset, nPreGrant, DoGrant, DoShift -- in -- =BIT, Grant, Shift -- out -- =BIT, Vdd, Gnd=BIT, BiasMinus, BiasPlus -- in -- =BIAS] Expand l1: InvertingLatchWithPreset[Clock: DoGrant, nPreset: nReset, D: nPreGrant, nQ: Grant]; l2: InvertingLatchWithPreset[Clock: DoShift, nPreset: nReset, D: nPreGrant, nQ: Shift] EndCellType