
<<Gates.Rose>>
<<Copyright (C) 1984 by Xerox Corp.  All rights reserved.>>
<<Last Edited by: Gasbarro, July 31, 1984 3:43:51 pm PDT>>

Library Transistors;

CellType "Inverter"
PORTS [in -- in -- =BIT, out=BIT, Vdd, Gnd=BIT]
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pu1: pE[gate: in, ch1: Vdd, ch2: out];
pd1: nE[gate: in, ch1: Gnd, ch2: out]
EndCellType;

CellType "NAND"
PORTS [in1, in2 -- in -- =BIT, out=BIT, Vdd, Gnd=BIT]
Expand
t1: BIT;
pu1: pE[gate: in1, ch1: Vdd, ch2: out];
pu2: pE[gate: in2, ch1: Vdd, ch2: out];
pd1: nE[gate: in1, ch1: t1, ch2: out];
pd2: nE[gate: in2, ch1: Gnd, ch2: t1]
EndCellType;

CellType "NOR"
PORTS [in1, in2 -- in -- =BIT, out=BIT, Vdd, Gnd=BIT]
Expand
t1: BIT;
pu1: pE[gate: in1, ch1: Vdd, ch2: t1];
pu2: pE[gate: in2, ch1: t1, ch2: out];
pd1: nE[gate: in1, ch1: Gnd, ch2: out];
pd2: nE[gate: in2, ch1: Gnd, ch2: out]
EndCellType;

CellType "OAI"
PORTS [ino1, ino2, ina1 -- in -- =BIT, out=BIT, Vdd, Gnd=BIT]
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t1, t2: BIT;
pu1: pE[gate: ino1, ch1: Vdd, ch2: t1];
pu2: pE[gate: ino2, ch1: t1, ch2: out];
pu3: pE[gate: ina1, ch1: Vdd, ch2: out];

pd1: nE[gate: ino1, ch1: Gnd, ch2: t2];
pd2: nE[gate: ino2, ch1: Gnd, ch2: t2];
pd3: nE[gate: ina1, ch1: t2, ch2: out]
EndCellType;

CellType "StaticPrecharge"
PORTS [clock -- in -- =BIT, out=BIT, Vdd, Gnd -- in -- =BIT, BiasPlus=BIAS]
Expand
s1: pE[gate: clock, ch1: Vdd, ch2: out];
s2: Transistor[positive: FALSE, unidirectional: TRUE, biased: TRUE, offStrength: driveWeak][gate: BiasPlus, ch1: Vdd, ch2: out]
EndCellType