<> <> <> <> <<>> Library Gates, Latches, Transistors; CellType "DoDrive" PORTS [NewRequest, nPhA, PhB -- in -- =BIT, Keep, NoRequest=BIT, DoGrant, DoShift -- out -- =BIT, Vdd, Gnd=BIT, BiasMinus, BiasPlus -- in -- =BIAS] Expand t1, t2, t3, t4, t5, t6, t7, t8: BIT; i1: Inverter[in: NewRequest, out: t1]; i2: Inverter[in: t1, out: t2]; s1: StaticPrecharge[clock: nPhA, out: Keep]; g1: NOR[in1: Keep, in2: t2, out: t3]; s2: StaticPrecharge[clock: nPhA, out: NoRequest]; g2: NOR[in1: NoRequest, in2: t3, out: t4]; i3: Inverter[in: t4, out: t5]; l1: WeakNonInvertingLatch[Clock: PhB, D: t3, Q: t6]; g3: NOR[in1: t6, in2: nPhA, out: DoGrant]; l2: WeakNonInvertingLatch[Clock: PhB, D: t5, Q: t7]; g4: NOR[in1: t7, in2: nPhA, out: DoShift] EndCellType