<> <> <> <> <<>> IMPORTS RoseCreate; Library Gates, Latches, Transistors; CellType "BiasGen" PORTS [Vdd, Gnd=BIT, BiasMinus, BiasPlus -- out -- =BIAS] EvalSimple BiasMinus _ Minus; BiasPlus _ Plus; Expand bp, bn: BIT+X _ "X"; t1: pE[gate: bp, ch1: Vdd, ch2: bp]; t2: nE[gate: Vdd, ch1: Gnd, ch2: bp]; t3: pE[gate: Gnd, ch1: Vdd, ch2: bn]; t4: nE[gate: bn, ch1: Gnd, ch2: bn]; CEDAR to.class.ChangeReps[erInstance: to.instance, a: bp, b: BiasPlus, writeA: FALSE, writeB: TRUE]; to.class.ChangeReps[erInstance: to.instance, a: bn, b: BiasMinus, writeA: FALSE, writeB: TRUE]; EndCellType <<>>