BiasGen.Rose
Copyright (C) 1984 by Xerox Corp. All rights reserved.
Last Edited by: Gasbarro, August 16, 1984 3:16:31 pm PDT
Last Edited by: Spreitzer, August 18, 1984 10:44:28 pm PDT
IMPORTS RoseCreate;
Library Gates, Latches, Transistors;
CellType "BiasGen"
PORTS [Vdd, Gnd=BIT, BiasMinus, BiasPlus -- out -- =BIAS]
EvalSimple
BiasMinus ← Minus;
BiasPlus ← Plus;
Expand
bp, bn: BIT+X ← "X";
t1: pE[gate: bp, ch1: Vdd, ch2: bp];
t2: nE[gate: Vdd, ch1: Gnd, ch2: bp];
t3: pE[gate: Gnd, ch1: Vdd, ch2: bn];
t4: nE[gate: bn, ch1: Gnd, ch2: bn];
CEDAR
to.class.ChangeReps[erInstance: to.instance, a: bp, b: BiasPlus, writeA: FALSE, writeB: TRUE];
to.class.ChangeReps[erInstance: to.instance, a: bn, b: BiasMinus, writeA: FALSE, writeB: TRUE];
EndCellType