CIRCUIT[Lambda _ 1.0, Temp _ 25] = { Vdd: node; powerSupply: voltage[Vdd, Gnd]= 5.00; ! ThymeBasics.thy ! CMos2.0u100C.thy -- process file -- N o d e s AIn, nAIn: node; PhA, nPhA: node; N1, N2, N3, N4, N5, N6, N7, N8, N9: node; Q1: CTran[AIn,N1,N2|L_2,W_500]; Q2: CTran[nAIn,N1,N3|L_2,W_500]; Q5: CTran[N4,Vdd,N1|L_2,W_1000]; Q6: ETran[N3,nPhA,Gnd|L_2,W_200]; Q7: CTran[N3,Vdd,nPhA|L_2,W_500]; Q8: CTran[N4,Vdd,N4|L_2,W_50]; Q9: ETran[nPhA,PhA,Gnd|L_2,W_800]; Q10: CTran[nPhA,Vdd,PhA|L_2,W_2000]; Q11: ETran[Vdd,N4,N9|L_4, W_8]; R1: resistor[N2,N7] = 1K; R2: resistor[N3,N8] = 1K; C1: capacitor[PhA,Gnd] = 50pF; V1: voltage[N7,Gnd] = 0; V2: voltage[N8,Gnd] = 0; V3: voltage[N9,Gnd] = 0; ?: RectWave[AIn|OnLevel_ 4V, OffLevel_ 3.0V, period_ 50ns, width_ 25ns, tRise_ 2ns, tFall_ 2ns, tDelay_ 10ns]; ?: RectWave[nAIn|OnLevel_ 3.0V, OffLevel_ 4V, period_ 50ns, width_ 25ns, tRise_ 2ns, tFall_ 2ns, tDelay_ 10ns]; }; plot["CMOS Clock Buffer, 1K passive load, 100C, of September 7, 1984 4:11:08 pm PDT", : 1ns, -1, 6, AIn, nAIn, N2, N3, nPhA, PhA, powerSupply^: -10mA, V1^: 1.2mA, V2^: 1.2mA, V3^: 1mA]; run[tMax _ 60ns, maxIter _ 2000]; ŽECLTranslator.thy Dragon Clock buffer circuit Last Edited by: Gasbarro, September 7, 1984 4:11:38 pm PDT Q3: ETran[N2,N2,N7|L_2,W_100]; Q4: ETran[N2,N3,N8|L_2,W_100]; Ęź˜J™J™J™:J˜JšĎkœ˜$J˜J˜ J˜&J˜J˜J˜#J˜J˜ J˜J˜J˜*J˜J˜J˜ J™J™J˜ J˜!J˜!J˜J˜"J˜$J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜˜SJ˜—˜TJ˜—J˜J˜J˜J˜šJ˜!J˜J˜J˜—…—„î